2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
150 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
151 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
154 #define NUL0E L0_ENTRIES
155 #define NUL1E (NUL0E * NL1PG)
156 #define NUL2E (NUL1E * NL2PG)
158 #if !defined(DIAGNOSTIC)
159 #ifdef __GNUC_GNU_INLINE__
160 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
162 #define PMAP_INLINE extern inline
169 * These are configured by the mair_el1 register. This is set up in locore.S
171 #define DEVICE_MEMORY 0
172 #define UNCACHED_MEMORY 1
173 #define CACHED_MEMORY 2
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
185 #define NPV_LIST_LOCKS MAXCPU
187 #define PHYS_TO_PV_LIST_LOCK(pa) \
188 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
190 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
191 struct rwlock **_lockp = (lockp); \
192 struct rwlock *_new_lock; \
194 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
195 if (_new_lock != *_lockp) { \
196 if (*_lockp != NULL) \
197 rw_wunlock(*_lockp); \
198 *_lockp = _new_lock; \
203 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
204 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
206 #define RELEASE_PV_LIST_LOCK(lockp) do { \
207 struct rwlock **_lockp = (lockp); \
209 if (*_lockp != NULL) { \
210 rw_wunlock(*_lockp); \
215 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
216 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
218 struct pmap kernel_pmap_store;
220 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
221 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
222 vm_offset_t kernel_vm_end = 0;
225 * Data for the pv entry allocation mechanism.
226 * Updates to pv_invl_gen are protected by the pv_list_locks[]
227 * elements, but reads are not.
229 static struct md_page *pv_table;
230 static struct md_page pv_dummy;
232 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
233 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
234 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
236 /* This code assumes all L1 DMAP entries will be used */
237 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
238 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
240 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
241 extern pt_entry_t pagetable_dmap[];
243 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
245 static int superpages_enabled = 1;
246 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
247 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
248 "Are large page mappings enabled?");
251 * Data for the pv entry allocation mechanism
253 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
254 static struct mtx pv_chunks_mutex;
255 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
257 static void free_pv_chunk(struct pv_chunk *pc);
258 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
259 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
260 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
261 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
262 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
265 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
266 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
267 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
268 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
269 vm_offset_t va, struct rwlock **lockp);
270 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
271 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
272 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
273 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
274 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
275 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
276 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
277 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
278 vm_page_t m, struct rwlock **lockp);
280 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
281 struct rwlock **lockp);
283 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
284 struct spglist *free);
285 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
286 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
289 * These load the old table data and store the new value.
290 * They need to be atomic as the System MMU may write to the table at
291 * the same time as the CPU.
293 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
294 #define pmap_set(table, mask) atomic_set_64(table, mask)
295 #define pmap_load_clear(table) atomic_swap_64(table, 0)
296 #define pmap_load(table) (*table)
298 /********************/
299 /* Inline functions */
300 /********************/
303 pagecopy(void *s, void *d)
306 memcpy(d, s, PAGE_SIZE);
309 static __inline pd_entry_t *
310 pmap_l0(pmap_t pmap, vm_offset_t va)
313 return (&pmap->pm_l0[pmap_l0_index(va)]);
316 static __inline pd_entry_t *
317 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
321 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
322 return (&l1[pmap_l1_index(va)]);
325 static __inline pd_entry_t *
326 pmap_l1(pmap_t pmap, vm_offset_t va)
330 l0 = pmap_l0(pmap, va);
331 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
334 return (pmap_l0_to_l1(l0, va));
337 static __inline pd_entry_t *
338 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
342 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
343 return (&l2[pmap_l2_index(va)]);
346 static __inline pd_entry_t *
347 pmap_l2(pmap_t pmap, vm_offset_t va)
351 l1 = pmap_l1(pmap, va);
352 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
355 return (pmap_l1_to_l2(l1, va));
358 static __inline pt_entry_t *
359 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
363 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
364 return (&l3[pmap_l3_index(va)]);
368 * Returns the lowest valid pde for a given virtual address.
369 * The next level may or may not point to a valid page or block.
371 static __inline pd_entry_t *
372 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
374 pd_entry_t *l0, *l1, *l2, desc;
376 l0 = pmap_l0(pmap, va);
377 desc = pmap_load(l0) & ATTR_DESCR_MASK;
378 if (desc != L0_TABLE) {
383 l1 = pmap_l0_to_l1(l0, va);
384 desc = pmap_load(l1) & ATTR_DESCR_MASK;
385 if (desc != L1_TABLE) {
390 l2 = pmap_l1_to_l2(l1, va);
391 desc = pmap_load(l2) & ATTR_DESCR_MASK;
392 if (desc != L2_TABLE) {
402 * Returns the lowest valid pte block or table entry for a given virtual
403 * address. If there are no valid entries return NULL and set the level to
404 * the first invalid level.
406 static __inline pt_entry_t *
407 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
409 pd_entry_t *l1, *l2, desc;
412 l1 = pmap_l1(pmap, va);
417 desc = pmap_load(l1) & ATTR_DESCR_MASK;
418 if (desc == L1_BLOCK) {
423 if (desc != L1_TABLE) {
428 l2 = pmap_l1_to_l2(l1, va);
429 desc = pmap_load(l2) & ATTR_DESCR_MASK;
430 if (desc == L2_BLOCK) {
435 if (desc != L2_TABLE) {
441 l3 = pmap_l2_to_l3(l2, va);
442 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
449 pmap_superpages_enabled(void)
452 return (superpages_enabled != 0);
456 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
457 pd_entry_t **l2, pt_entry_t **l3)
459 pd_entry_t *l0p, *l1p, *l2p;
461 if (pmap->pm_l0 == NULL)
464 l0p = pmap_l0(pmap, va);
467 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
470 l1p = pmap_l0_to_l1(l0p, va);
473 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
479 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
482 l2p = pmap_l1_to_l2(l1p, va);
485 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
490 *l3 = pmap_l2_to_l3(l2p, va);
496 pmap_l3_valid(pt_entry_t l3)
499 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
503 CTASSERT(L1_BLOCK == L2_BLOCK);
506 * Checks if the page is dirty. We currently lack proper tracking of this on
507 * arm64 so for now assume is a page mapped as rw was accessed it is.
510 pmap_page_dirty(pt_entry_t pte)
513 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
514 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
518 pmap_resident_count_inc(pmap_t pmap, int count)
521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
522 pmap->pm_stats.resident_count += count;
526 pmap_resident_count_dec(pmap_t pmap, int count)
529 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
530 KASSERT(pmap->pm_stats.resident_count >= count,
531 ("pmap %p resident count underflow %ld %d", pmap,
532 pmap->pm_stats.resident_count, count));
533 pmap->pm_stats.resident_count -= count;
537 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
543 l1 = (pd_entry_t *)l1pt;
544 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
546 /* Check locore has used a table L1 map */
547 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
548 ("Invalid bootstrap L1 table"));
549 /* Find the address of the L2 table */
550 l2 = (pt_entry_t *)init_pt_va;
551 *l2_slot = pmap_l2_index(va);
557 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
559 u_int l1_slot, l2_slot;
562 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
564 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
568 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
575 dmap_phys_base = min_pa & ~L1_OFFSET;
579 for (i = 0; i < (physmap_idx * 2); i += 2) {
580 pa = physmap[i] & ~L1_OFFSET;
581 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
583 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
584 pa += L1_SIZE, va += L1_SIZE) {
585 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
586 /* We already have an entry */
587 if (pagetable_dmap[l1_slot] != 0)
589 pmap_load_store(&pagetable_dmap[l1_slot],
590 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
591 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
594 if (pa > dmap_phys_max) {
604 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
611 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
613 l1 = (pd_entry_t *)l1pt;
614 l1_slot = pmap_l1_index(va);
617 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
618 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
620 pa = pmap_early_vtophys(l1pt, l2pt);
621 pmap_load_store(&l1[l1_slot],
622 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
626 /* Clean the L2 page table */
627 memset((void *)l2_start, 0, l2pt - l2_start);
633 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
640 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
642 l2 = pmap_l2(kernel_pmap, va);
643 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
644 l2_slot = pmap_l2_index(va);
647 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
648 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
650 pa = pmap_early_vtophys(l1pt, l3pt);
651 pmap_load_store(&l2[l2_slot],
652 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
656 /* Clean the L2 page table */
657 memset((void *)l3_start, 0, l3pt - l3_start);
663 * Bootstrap the system enough to run with virtual memory.
666 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
669 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
672 vm_offset_t va, freemempos;
673 vm_offset_t dpcpu, msgbufpv;
674 vm_paddr_t pa, max_pa, min_pa;
677 kern_delta = KERNBASE - kernstart;
680 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
681 printf("%lx\n", l1pt);
682 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
684 /* Set this early so we can use the pagetable walking functions */
685 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
686 PMAP_LOCK_INIT(kernel_pmap);
688 /* Assume the address we were loaded to is a valid physical address */
689 min_pa = max_pa = KERNBASE - kern_delta;
692 * Find the minimum physical address. physmap is sorted,
693 * but may contain empty ranges.
695 for (i = 0; i < (physmap_idx * 2); i += 2) {
696 if (physmap[i] == physmap[i + 1])
698 if (physmap[i] <= min_pa)
700 if (physmap[i + 1] > max_pa)
701 max_pa = physmap[i + 1];
704 /* Create a direct map region early so we can use it for pa -> va */
705 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
708 pa = KERNBASE - kern_delta;
711 * Start to initialise phys_avail by copying from physmap
712 * up to the physical address KERNBASE points at.
714 map_slot = avail_slot = 0;
715 for (; map_slot < (physmap_idx * 2) &&
716 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
717 if (physmap[map_slot] == physmap[map_slot + 1])
720 if (physmap[map_slot] <= pa &&
721 physmap[map_slot + 1] > pa)
724 phys_avail[avail_slot] = physmap[map_slot];
725 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
726 physmem += (phys_avail[avail_slot + 1] -
727 phys_avail[avail_slot]) >> PAGE_SHIFT;
731 /* Add the memory before the kernel */
732 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
733 phys_avail[avail_slot] = physmap[map_slot];
734 phys_avail[avail_slot + 1] = pa;
735 physmem += (phys_avail[avail_slot + 1] -
736 phys_avail[avail_slot]) >> PAGE_SHIFT;
739 used_map_slot = map_slot;
742 * Read the page table to find out what is already mapped.
743 * This assumes we have mapped a block of memory from KERNBASE
744 * using a single L1 entry.
746 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
748 /* Sanity check the index, KERNBASE should be the first VA */
749 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
751 /* Find how many pages we have mapped */
752 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
753 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
756 /* Check locore used L2 blocks */
757 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
758 ("Invalid bootstrap L2 table"));
759 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
760 ("Incorrect PA in L2 table"));
766 va = roundup2(va, L1_SIZE);
768 freemempos = KERNBASE + kernlen;
769 freemempos = roundup2(freemempos, PAGE_SIZE);
770 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
771 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
772 /* And the l3 tables for the early devmap */
773 freemempos = pmap_bootstrap_l3(l1pt,
774 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
778 #define alloc_pages(var, np) \
779 (var) = freemempos; \
780 freemempos += (np * PAGE_SIZE); \
781 memset((char *)(var), 0, ((np) * PAGE_SIZE));
783 /* Allocate dynamic per-cpu area. */
784 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
785 dpcpu_init((void *)dpcpu, 0);
787 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
788 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
789 msgbufp = (void *)msgbufpv;
791 virtual_avail = roundup2(freemempos, L1_SIZE);
792 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
793 kernel_vm_end = virtual_avail;
795 pa = pmap_early_vtophys(l1pt, freemempos);
797 /* Finish initialising physmap */
798 map_slot = used_map_slot;
799 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
800 map_slot < (physmap_idx * 2); map_slot += 2) {
801 if (physmap[map_slot] == physmap[map_slot + 1])
804 /* Have we used the current range? */
805 if (physmap[map_slot + 1] <= pa)
808 /* Do we need to split the entry? */
809 if (physmap[map_slot] < pa) {
810 phys_avail[avail_slot] = pa;
811 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
813 phys_avail[avail_slot] = physmap[map_slot];
814 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
816 physmem += (phys_avail[avail_slot + 1] -
817 phys_avail[avail_slot]) >> PAGE_SHIFT;
821 phys_avail[avail_slot] = 0;
822 phys_avail[avail_slot + 1] = 0;
825 * Maxmem isn't the "maximum memory", it's one larger than the
826 * highest page of the physical address space. It should be
827 * called something like "Maxphyspage".
829 Maxmem = atop(phys_avail[avail_slot - 1]);
835 * Initialize a vm_page's machine-dependent fields.
838 pmap_page_init(vm_page_t m)
841 TAILQ_INIT(&m->md.pv_list);
842 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
846 * Initialize the pmap module.
847 * Called by vm_init, to initialize any structures that the pmap
848 * system needs to map virtual memory.
857 * Are large page mappings enabled?
859 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
862 * Initialize the pv chunk list mutex.
864 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
867 * Initialize the pool of pv list locks.
869 for (i = 0; i < NPV_LIST_LOCKS; i++)
870 rw_init(&pv_list_locks[i], "pmap pv list");
873 * Calculate the size of the pv head table for superpages.
875 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
878 * Allocate memory for the pv head table for superpages.
880 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
882 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
884 for (i = 0; i < pv_npg; i++)
885 TAILQ_INIT(&pv_table[i].pv_list);
886 TAILQ_INIT(&pv_dummy.pv_list);
889 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
890 "2MB page mapping counters");
892 static u_long pmap_l2_demotions;
893 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
894 &pmap_l2_demotions, 0, "2MB page demotions");
896 static u_long pmap_l2_p_failures;
897 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
898 &pmap_l2_p_failures, 0, "2MB page promotion failures");
900 static u_long pmap_l2_promotions;
901 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
902 &pmap_l2_promotions, 0, "2MB page promotions");
905 * Invalidate a single TLB entry.
908 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
914 "tlbi vaae1is, %0 \n"
917 : : "r"(va >> PAGE_SHIFT));
922 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
927 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
929 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
937 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
941 pmap_invalidate_range_nopin(pmap, sva, eva);
946 pmap_invalidate_all(pmap_t pmap)
959 * Routine: pmap_extract
961 * Extract the physical page address associated
962 * with the given map/virtual_address pair.
965 pmap_extract(pmap_t pmap, vm_offset_t va)
967 pt_entry_t *pte, tpte;
974 * Find the block or page map for this virtual address. pmap_pte
975 * will return either a valid block/page entry, or NULL.
977 pte = pmap_pte(pmap, va, &lvl);
979 tpte = pmap_load(pte);
980 pa = tpte & ~ATTR_MASK;
983 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
984 ("pmap_extract: Invalid L1 pte found: %lx",
985 tpte & ATTR_DESCR_MASK));
986 pa |= (va & L1_OFFSET);
989 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
990 ("pmap_extract: Invalid L2 pte found: %lx",
991 tpte & ATTR_DESCR_MASK));
992 pa |= (va & L2_OFFSET);
995 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
996 ("pmap_extract: Invalid L3 pte found: %lx",
997 tpte & ATTR_DESCR_MASK));
998 pa |= (va & L3_OFFSET);
1007 * Routine: pmap_extract_and_hold
1009 * Atomically extract and hold the physical page
1010 * with the given pmap and virtual address pair
1011 * if that mapping permits the given protection.
1014 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1016 pt_entry_t *pte, tpte;
1026 pte = pmap_pte(pmap, va, &lvl);
1028 tpte = pmap_load(pte);
1030 KASSERT(lvl > 0 && lvl <= 3,
1031 ("pmap_extract_and_hold: Invalid level %d", lvl));
1032 CTASSERT(L1_BLOCK == L2_BLOCK);
1033 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1034 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1035 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1036 tpte & ATTR_DESCR_MASK));
1037 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1038 ((prot & VM_PROT_WRITE) == 0)) {
1041 off = va & L1_OFFSET;
1044 off = va & L2_OFFSET;
1050 if (vm_page_pa_tryrelock(pmap,
1051 (tpte & ~ATTR_MASK) | off, &pa))
1053 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1063 pmap_kextract(vm_offset_t va)
1065 pt_entry_t *pte, tpte;
1069 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1070 pa = DMAP_TO_PHYS(va);
1073 pte = pmap_pte(kernel_pmap, va, &lvl);
1075 tpte = pmap_load(pte);
1076 pa = tpte & ~ATTR_MASK;
1079 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1080 ("pmap_kextract: Invalid L1 pte found: %lx",
1081 tpte & ATTR_DESCR_MASK));
1082 pa |= (va & L1_OFFSET);
1085 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1086 ("pmap_kextract: Invalid L2 pte found: %lx",
1087 tpte & ATTR_DESCR_MASK));
1088 pa |= (va & L2_OFFSET);
1091 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1092 ("pmap_kextract: Invalid L3 pte found: %lx",
1093 tpte & ATTR_DESCR_MASK));
1094 pa |= (va & L3_OFFSET);
1102 /***************************************************
1103 * Low level mapping routines.....
1104 ***************************************************/
1107 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1110 pt_entry_t *pte, attr;
1114 KASSERT((pa & L3_OFFSET) == 0,
1115 ("pmap_kenter: Invalid physical address"));
1116 KASSERT((sva & L3_OFFSET) == 0,
1117 ("pmap_kenter: Invalid virtual address"));
1118 KASSERT((size & PAGE_MASK) == 0,
1119 ("pmap_kenter: Mapping is not page-sized"));
1121 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1122 if (mode == DEVICE_MEMORY)
1127 pde = pmap_pde(kernel_pmap, va, &lvl);
1128 KASSERT(pde != NULL,
1129 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1130 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1132 pte = pmap_l2_to_l3(pde, va);
1133 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1139 pmap_invalidate_range(kernel_pmap, sva, va);
1143 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1146 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1150 * Remove a page from the kernel pagetables.
1153 pmap_kremove(vm_offset_t va)
1158 pte = pmap_pte(kernel_pmap, va, &lvl);
1159 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1160 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1162 pmap_load_clear(pte);
1163 pmap_invalidate_page(kernel_pmap, va);
1167 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1173 KASSERT((sva & L3_OFFSET) == 0,
1174 ("pmap_kremove_device: Invalid virtual address"));
1175 KASSERT((size & PAGE_MASK) == 0,
1176 ("pmap_kremove_device: Mapping is not page-sized"));
1180 pte = pmap_pte(kernel_pmap, va, &lvl);
1181 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1183 ("Invalid device pagetable level: %d != 3", lvl));
1184 pmap_load_clear(pte);
1189 pmap_invalidate_range(kernel_pmap, sva, va);
1193 * Used to map a range of physical addresses into kernel
1194 * virtual address space.
1196 * The value passed in '*virt' is a suggested virtual address for
1197 * the mapping. Architectures which can support a direct-mapped
1198 * physical to virtual region can return the appropriate address
1199 * within that region, leaving '*virt' unchanged. Other
1200 * architectures should map the pages starting at '*virt' and
1201 * update '*virt' with the first usable address after the mapped
1205 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1207 return PHYS_TO_DMAP(start);
1212 * Add a list of wired pages to the kva
1213 * this routine is only used for temporary
1214 * kernel mappings that do not need to have
1215 * page modification or references recorded.
1216 * Note that old mappings are simply written
1217 * over. The page *must* be wired.
1218 * Note: SMP coherent. Uses a ranged shootdown IPI.
1221 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1224 pt_entry_t *pte, pa;
1230 for (i = 0; i < count; i++) {
1231 pde = pmap_pde(kernel_pmap, va, &lvl);
1232 KASSERT(pde != NULL,
1233 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1235 ("pmap_qenter: Invalid level %d", lvl));
1238 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1239 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1240 if (m->md.pv_memattr == DEVICE_MEMORY)
1242 pte = pmap_l2_to_l3(pde, va);
1243 pmap_load_store(pte, pa);
1247 pmap_invalidate_range(kernel_pmap, sva, va);
1251 * This routine tears out page mappings from the
1252 * kernel -- it is meant only for temporary mappings.
1255 pmap_qremove(vm_offset_t sva, int count)
1261 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1264 while (count-- > 0) {
1265 pte = pmap_pte(kernel_pmap, va, &lvl);
1267 ("Invalid device pagetable level: %d != 3", lvl));
1269 pmap_load_clear(pte);
1274 pmap_invalidate_range(kernel_pmap, sva, va);
1277 /***************************************************
1278 * Page table page management routines.....
1279 ***************************************************/
1281 * Schedule the specified unused page table page to be freed. Specifically,
1282 * add the page to the specified list of pages that will be released to the
1283 * physical memory manager after the TLB has been updated.
1285 static __inline void
1286 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1287 boolean_t set_PG_ZERO)
1291 m->flags |= PG_ZERO;
1293 m->flags &= ~PG_ZERO;
1294 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1298 * Decrements a page table page's wire count, which is used to record the
1299 * number of valid page table entries within the page. If the wire count
1300 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1301 * page table page was unmapped and FALSE otherwise.
1303 static inline boolean_t
1304 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1308 if (m->wire_count == 0) {
1309 _pmap_unwire_l3(pmap, va, m, free);
1316 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1319 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1321 * unmap the page table page
1323 if (m->pindex >= (NUL2E + NUL1E)) {
1327 l0 = pmap_l0(pmap, va);
1328 pmap_load_clear(l0);
1329 } else if (m->pindex >= NUL2E) {
1333 l1 = pmap_l1(pmap, va);
1334 pmap_load_clear(l1);
1339 l2 = pmap_l2(pmap, va);
1340 pmap_load_clear(l2);
1342 pmap_resident_count_dec(pmap, 1);
1343 if (m->pindex < NUL2E) {
1344 /* We just released an l3, unhold the matching l2 */
1345 pd_entry_t *l1, tl1;
1348 l1 = pmap_l1(pmap, va);
1349 tl1 = pmap_load(l1);
1350 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1351 pmap_unwire_l3(pmap, va, l2pg, free);
1352 } else if (m->pindex < (NUL2E + NUL1E)) {
1353 /* We just released an l2, unhold the matching l1 */
1354 pd_entry_t *l0, tl0;
1357 l0 = pmap_l0(pmap, va);
1358 tl0 = pmap_load(l0);
1359 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1360 pmap_unwire_l3(pmap, va, l1pg, free);
1362 pmap_invalidate_page(pmap, va);
1367 * Put page on a list so that it is released after
1368 * *ALL* TLB shootdown is done
1370 pmap_add_delayed_free_list(m, free, TRUE);
1374 * After removing a page table entry, this routine is used to
1375 * conditionally free the page, and manage the hold/wire counts.
1378 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1379 struct spglist *free)
1383 if (va >= VM_MAXUSER_ADDRESS)
1385 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1386 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1387 return (pmap_unwire_l3(pmap, va, mpte, free));
1391 pmap_pinit0(pmap_t pmap)
1394 PMAP_LOCK_INIT(pmap);
1395 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1396 pmap->pm_l0 = kernel_pmap->pm_l0;
1397 pmap->pm_root.rt_root = 0;
1401 pmap_pinit(pmap_t pmap)
1407 * allocate the l0 page
1409 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1410 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1413 l0phys = VM_PAGE_TO_PHYS(l0pt);
1414 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1416 if ((l0pt->flags & PG_ZERO) == 0)
1417 pagezero(pmap->pm_l0);
1419 pmap->pm_root.rt_root = 0;
1420 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1426 * This routine is called if the desired page table page does not exist.
1428 * If page table page allocation fails, this routine may sleep before
1429 * returning NULL. It sleeps only if a lock pointer was given.
1431 * Note: If a page allocation fails at page table level two or three,
1432 * one or two pages may be held during the wait, only to be released
1433 * afterwards. This conservative approach is easily argued to avoid
1437 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1439 vm_page_t m, l1pg, l2pg;
1441 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1444 * Allocate a page table page.
1446 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1447 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1448 if (lockp != NULL) {
1449 RELEASE_PV_LIST_LOCK(lockp);
1456 * Indicate the need to retry. While waiting, the page table
1457 * page may have been allocated.
1461 if ((m->flags & PG_ZERO) == 0)
1465 * Map the pagetable page into the process address space, if
1466 * it isn't already there.
1469 if (ptepindex >= (NUL2E + NUL1E)) {
1471 vm_pindex_t l0index;
1473 l0index = ptepindex - (NUL2E + NUL1E);
1474 l0 = &pmap->pm_l0[l0index];
1475 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1476 } else if (ptepindex >= NUL2E) {
1477 vm_pindex_t l0index, l1index;
1478 pd_entry_t *l0, *l1;
1481 l1index = ptepindex - NUL2E;
1482 l0index = l1index >> L0_ENTRIES_SHIFT;
1484 l0 = &pmap->pm_l0[l0index];
1485 tl0 = pmap_load(l0);
1487 /* recurse for allocating page dir */
1488 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1490 vm_page_unwire_noq(m);
1491 vm_page_free_zero(m);
1495 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1499 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1500 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1501 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1503 vm_pindex_t l0index, l1index;
1504 pd_entry_t *l0, *l1, *l2;
1505 pd_entry_t tl0, tl1;
1507 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1508 l0index = l1index >> L0_ENTRIES_SHIFT;
1510 l0 = &pmap->pm_l0[l0index];
1511 tl0 = pmap_load(l0);
1513 /* recurse for allocating page dir */
1514 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1516 vm_page_unwire_noq(m);
1517 vm_page_free_zero(m);
1520 tl0 = pmap_load(l0);
1521 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1522 l1 = &l1[l1index & Ln_ADDR_MASK];
1524 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1525 l1 = &l1[l1index & Ln_ADDR_MASK];
1526 tl1 = pmap_load(l1);
1528 /* recurse for allocating page dir */
1529 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1531 vm_page_unwire_noq(m);
1532 vm_page_free_zero(m);
1536 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1541 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1542 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1543 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1546 pmap_resident_count_inc(pmap, 1);
1552 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1554 vm_pindex_t ptepindex;
1555 pd_entry_t *pde, tpde;
1563 * Calculate pagetable page index
1565 ptepindex = pmap_l2_pindex(va);
1568 * Get the page directory entry
1570 pde = pmap_pde(pmap, va, &lvl);
1573 * If the page table page is mapped, we just increment the hold count,
1574 * and activate it. If we get a level 2 pde it will point to a level 3
1582 pte = pmap_l0_to_l1(pde, va);
1583 KASSERT(pmap_load(pte) == 0,
1584 ("pmap_alloc_l3: TODO: l0 superpages"));
1589 pte = pmap_l1_to_l2(pde, va);
1590 KASSERT(pmap_load(pte) == 0,
1591 ("pmap_alloc_l3: TODO: l1 superpages"));
1595 tpde = pmap_load(pde);
1597 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1603 panic("pmap_alloc_l3: Invalid level %d", lvl);
1607 * Here if the pte page isn't mapped, or if it has been deallocated.
1609 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1610 if (m == NULL && lockp != NULL)
1617 /***************************************************
1618 * Pmap allocation/deallocation routines.
1619 ***************************************************/
1622 * Release any resources held by the given physical map.
1623 * Called when a pmap initialized by pmap_pinit is being released.
1624 * Should only be called if the map contains no valid mappings.
1627 pmap_release(pmap_t pmap)
1631 KASSERT(pmap->pm_stats.resident_count == 0,
1632 ("pmap_release: pmap resident count %ld != 0",
1633 pmap->pm_stats.resident_count));
1634 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1635 ("pmap_release: pmap has reserved page table page(s)"));
1637 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1639 vm_page_unwire_noq(m);
1640 vm_page_free_zero(m);
1644 kvm_size(SYSCTL_HANDLER_ARGS)
1646 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1648 return sysctl_handle_long(oidp, &ksize, 0, req);
1650 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1651 0, 0, kvm_size, "LU", "Size of KVM");
1654 kvm_free(SYSCTL_HANDLER_ARGS)
1656 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1658 return sysctl_handle_long(oidp, &kfree, 0, req);
1660 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1661 0, 0, kvm_free, "LU", "Amount of KVM free");
1664 * grow the number of kernel page table entries, if needed
1667 pmap_growkernel(vm_offset_t addr)
1671 pd_entry_t *l0, *l1, *l2;
1673 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1675 addr = roundup2(addr, L2_SIZE);
1676 if (addr - 1 >= kernel_map->max_offset)
1677 addr = kernel_map->max_offset;
1678 while (kernel_vm_end < addr) {
1679 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1680 KASSERT(pmap_load(l0) != 0,
1681 ("pmap_growkernel: No level 0 kernel entry"));
1683 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1684 if (pmap_load(l1) == 0) {
1685 /* We need a new PDP entry */
1686 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1687 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1688 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1690 panic("pmap_growkernel: no memory to grow kernel");
1691 if ((nkpg->flags & PG_ZERO) == 0)
1692 pmap_zero_page(nkpg);
1693 paddr = VM_PAGE_TO_PHYS(nkpg);
1694 pmap_load_store(l1, paddr | L1_TABLE);
1695 continue; /* try again */
1697 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1698 if ((pmap_load(l2) & ATTR_AF) != 0) {
1699 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1700 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1701 kernel_vm_end = kernel_map->max_offset;
1707 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1708 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1711 panic("pmap_growkernel: no memory to grow kernel");
1712 if ((nkpg->flags & PG_ZERO) == 0)
1713 pmap_zero_page(nkpg);
1714 paddr = VM_PAGE_TO_PHYS(nkpg);
1715 pmap_load_store(l2, paddr | L2_TABLE);
1716 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1718 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1719 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1720 kernel_vm_end = kernel_map->max_offset;
1727 /***************************************************
1728 * page management routines.
1729 ***************************************************/
1731 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1732 CTASSERT(_NPCM == 3);
1733 CTASSERT(_NPCPV == 168);
1735 static __inline struct pv_chunk *
1736 pv_to_chunk(pv_entry_t pv)
1739 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1742 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1744 #define PC_FREE0 0xfffffffffffffffful
1745 #define PC_FREE1 0xfffffffffffffffful
1746 #define PC_FREE2 0x000000fffffffffful
1748 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1752 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1754 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1755 "Current number of pv entry chunks");
1756 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1757 "Current number of pv entry chunks allocated");
1758 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1759 "Current number of pv entry chunks frees");
1760 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1761 "Number of times tried to get a chunk page but failed.");
1763 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1764 static int pv_entry_spare;
1766 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1767 "Current number of pv entry frees");
1768 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1769 "Current number of pv entry allocs");
1770 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1771 "Current number of pv entries");
1772 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1773 "Current number of spare pv entries");
1778 * We are in a serious low memory condition. Resort to
1779 * drastic measures to free some pages so we can allocate
1780 * another pv entry chunk.
1782 * Returns NULL if PV entries were reclaimed from the specified pmap.
1784 * We do not, however, unmap 2mpages because subsequent accesses will
1785 * allocate per-page pv entries until repromotion occurs, thereby
1786 * exacerbating the shortage of free pv entries.
1789 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1791 struct pch new_tail;
1792 struct pv_chunk *pc;
1793 struct md_page *pvh;
1796 pt_entry_t *pte, tpte;
1800 struct spglist free;
1802 int bit, field, freed, lvl;
1804 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1805 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1809 TAILQ_INIT(&new_tail);
1810 mtx_lock(&pv_chunks_mutex);
1811 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
1812 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1813 mtx_unlock(&pv_chunks_mutex);
1814 if (pmap != pc->pc_pmap) {
1815 if (pmap != NULL && pmap != locked_pmap)
1818 /* Avoid deadlock and lock recursion. */
1819 if (pmap > locked_pmap) {
1820 RELEASE_PV_LIST_LOCK(lockp);
1822 } else if (pmap != locked_pmap &&
1823 !PMAP_TRYLOCK(pmap)) {
1825 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1826 mtx_lock(&pv_chunks_mutex);
1832 * Destroy every non-wired, 4 KB page mapping in the chunk.
1835 for (field = 0; field < _NPCM; field++) {
1836 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1837 inuse != 0; inuse &= ~(1UL << bit)) {
1838 bit = ffsl(inuse) - 1;
1839 pv = &pc->pc_pventry[field * 64 + bit];
1841 pde = pmap_pde(pmap, va, &lvl);
1844 pte = pmap_l2_to_l3(pde, va);
1845 tpte = pmap_load(pte);
1846 if ((tpte & ATTR_SW_WIRED) != 0)
1848 tpte = pmap_load_clear(pte);
1849 pmap_invalidate_page(pmap, va);
1850 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1851 if (pmap_page_dirty(tpte))
1853 if ((tpte & ATTR_AF) != 0)
1854 vm_page_aflag_set(m, PGA_REFERENCED);
1855 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1856 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1858 if (TAILQ_EMPTY(&m->md.pv_list) &&
1859 (m->flags & PG_FICTITIOUS) == 0) {
1860 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1861 if (TAILQ_EMPTY(&pvh->pv_list)) {
1862 vm_page_aflag_clear(m,
1866 pc->pc_map[field] |= 1UL << bit;
1867 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1872 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1873 mtx_lock(&pv_chunks_mutex);
1876 /* Every freed mapping is for a 4 KB page. */
1877 pmap_resident_count_dec(pmap, freed);
1878 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1879 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1880 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1881 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1882 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1883 pc->pc_map[2] == PC_FREE2) {
1884 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1885 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1886 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1887 /* Entire chunk is free; return it. */
1888 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1889 dump_drop_page(m_pc->phys_addr);
1890 mtx_lock(&pv_chunks_mutex);
1893 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1894 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1895 mtx_lock(&pv_chunks_mutex);
1896 /* One freed pv entry in locked_pmap is sufficient. */
1897 if (pmap == locked_pmap)
1900 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
1901 mtx_unlock(&pv_chunks_mutex);
1902 if (pmap != NULL && pmap != locked_pmap)
1904 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
1905 m_pc = SLIST_FIRST(&free);
1906 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
1907 /* Recycle a freed page table page. */
1908 m_pc->wire_count = 1;
1911 vm_page_free_pages_toq(&free, false);
1916 * free the pv_entry back to the free list
1919 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1921 struct pv_chunk *pc;
1922 int idx, field, bit;
1924 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1925 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1926 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1927 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1928 pc = pv_to_chunk(pv);
1929 idx = pv - &pc->pc_pventry[0];
1932 pc->pc_map[field] |= 1ul << bit;
1933 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1934 pc->pc_map[2] != PC_FREE2) {
1935 /* 98% of the time, pc is already at the head of the list. */
1936 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1937 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1938 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1942 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1947 free_pv_chunk(struct pv_chunk *pc)
1951 mtx_lock(&pv_chunks_mutex);
1952 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1953 mtx_unlock(&pv_chunks_mutex);
1954 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1955 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1956 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1957 /* entire chunk is free, return it */
1958 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1959 dump_drop_page(m->phys_addr);
1960 vm_page_unwire_noq(m);
1965 * Returns a new PV entry, allocating a new PV chunk from the system when
1966 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1967 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1970 * The given PV list lock may be released.
1973 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1977 struct pv_chunk *pc;
1980 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1981 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1983 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1985 for (field = 0; field < _NPCM; field++) {
1986 if (pc->pc_map[field]) {
1987 bit = ffsl(pc->pc_map[field]) - 1;
1991 if (field < _NPCM) {
1992 pv = &pc->pc_pventry[field * 64 + bit];
1993 pc->pc_map[field] &= ~(1ul << bit);
1994 /* If this was the last item, move it to tail */
1995 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
1996 pc->pc_map[2] == 0) {
1997 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1998 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2001 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2002 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2006 /* No free items, allocate another chunk */
2007 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2010 if (lockp == NULL) {
2011 PV_STAT(pc_chunk_tryfail++);
2014 m = reclaim_pv_chunk(pmap, lockp);
2018 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2019 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2020 dump_add_page(m->phys_addr);
2021 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2023 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2024 pc->pc_map[1] = PC_FREE1;
2025 pc->pc_map[2] = PC_FREE2;
2026 mtx_lock(&pv_chunks_mutex);
2027 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2028 mtx_unlock(&pv_chunks_mutex);
2029 pv = &pc->pc_pventry[0];
2030 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2031 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2032 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2037 * Ensure that the number of spare PV entries in the specified pmap meets or
2038 * exceeds the given count, "needed".
2040 * The given PV list lock may be released.
2043 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2045 struct pch new_tail;
2046 struct pv_chunk *pc;
2050 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2051 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2054 * Newly allocated PV chunks must be stored in a private list until
2055 * the required number of PV chunks have been allocated. Otherwise,
2056 * reclaim_pv_chunk() could recycle one of these chunks. In
2057 * contrast, these chunks must be added to the pmap upon allocation.
2059 TAILQ_INIT(&new_tail);
2062 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2063 bit_count((bitstr_t *)pc->pc_map, 0,
2064 sizeof(pc->pc_map) * NBBY, &free);
2068 if (avail >= needed)
2071 for (; avail < needed; avail += _NPCPV) {
2072 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2075 m = reclaim_pv_chunk(pmap, lockp);
2079 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2080 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2081 dump_add_page(m->phys_addr);
2082 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2084 pc->pc_map[0] = PC_FREE0;
2085 pc->pc_map[1] = PC_FREE1;
2086 pc->pc_map[2] = PC_FREE2;
2087 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2088 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2089 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2091 if (!TAILQ_EMPTY(&new_tail)) {
2092 mtx_lock(&pv_chunks_mutex);
2093 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2094 mtx_unlock(&pv_chunks_mutex);
2099 * First find and then remove the pv entry for the specified pmap and virtual
2100 * address from the specified pv list. Returns the pv entry if found and NULL
2101 * otherwise. This operation can be performed on pv lists for either 4KB or
2102 * 2MB page mappings.
2104 static __inline pv_entry_t
2105 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2109 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2110 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2111 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2120 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2121 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2122 * entries for each of the 4KB page mappings.
2125 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2126 struct rwlock **lockp)
2128 struct md_page *pvh;
2129 struct pv_chunk *pc;
2131 vm_offset_t va_last;
2135 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2136 KASSERT((pa & L2_OFFSET) == 0,
2137 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2138 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2141 * Transfer the 2mpage's pv entry for this mapping to the first
2142 * page's pv list. Once this transfer begins, the pv list lock
2143 * must not be released until the last pv entry is reinstantiated.
2145 pvh = pa_to_pvh(pa);
2146 va = va & ~L2_OFFSET;
2147 pv = pmap_pvh_remove(pvh, pmap, va);
2148 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2149 m = PHYS_TO_VM_PAGE(pa);
2150 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2152 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2153 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2154 va_last = va + L2_SIZE - PAGE_SIZE;
2156 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2157 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2158 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2159 for (field = 0; field < _NPCM; field++) {
2160 while (pc->pc_map[field]) {
2161 bit = ffsl(pc->pc_map[field]) - 1;
2162 pc->pc_map[field] &= ~(1ul << bit);
2163 pv = &pc->pc_pventry[field * 64 + bit];
2167 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2168 ("pmap_pv_demote_l2: page %p is not managed", m));
2169 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2175 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2176 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2179 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2180 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2181 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2183 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2184 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2188 * First find and then destroy the pv entry for the specified pmap and virtual
2189 * address. This operation can be performed on pv lists for either 4KB or 2MB
2193 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2197 pv = pmap_pvh_remove(pvh, pmap, va);
2198 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2199 free_pv_entry(pmap, pv);
2203 * Conditionally create the PV entry for a 4KB page mapping if the required
2204 * memory can be allocated without resorting to reclamation.
2207 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2208 struct rwlock **lockp)
2212 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2213 /* Pass NULL instead of the lock pointer to disable reclamation. */
2214 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2216 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2217 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2225 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2228 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2229 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2231 struct md_page *pvh;
2233 vm_offset_t eva, va;
2236 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2237 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2238 old_l2 = pmap_load_clear(l2);
2239 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2240 if (old_l2 & ATTR_SW_WIRED)
2241 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2242 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2243 if (old_l2 & ATTR_SW_MANAGED) {
2244 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2245 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2246 pmap_pvh_free(pvh, pmap, sva);
2247 eva = sva + L2_SIZE;
2248 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2249 va < eva; va += PAGE_SIZE, m++) {
2250 if (pmap_page_dirty(old_l2))
2252 if (old_l2 & ATTR_AF)
2253 vm_page_aflag_set(m, PGA_REFERENCED);
2254 if (TAILQ_EMPTY(&m->md.pv_list) &&
2255 TAILQ_EMPTY(&pvh->pv_list))
2256 vm_page_aflag_clear(m, PGA_WRITEABLE);
2259 KASSERT(pmap != kernel_pmap,
2260 ("Attempting to remove an l2 kernel page"));
2261 ml3 = pmap_remove_pt_page(pmap, sva);
2263 pmap_resident_count_dec(pmap, 1);
2264 KASSERT(ml3->wire_count == NL3PG,
2265 ("pmap_remove_pages: l3 page wire count error"));
2266 ml3->wire_count = 1;
2267 vm_page_unwire_noq(ml3);
2268 pmap_add_delayed_free_list(ml3, free, FALSE);
2270 return (pmap_unuse_pt(pmap, sva, l1e, free));
2274 * pmap_remove_l3: do the things to unmap a page in a process
2277 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2278 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2280 struct md_page *pvh;
2284 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2285 old_l3 = pmap_load_clear(l3);
2286 pmap_invalidate_page(pmap, va);
2287 if (old_l3 & ATTR_SW_WIRED)
2288 pmap->pm_stats.wired_count -= 1;
2289 pmap_resident_count_dec(pmap, 1);
2290 if (old_l3 & ATTR_SW_MANAGED) {
2291 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2292 if (pmap_page_dirty(old_l3))
2294 if (old_l3 & ATTR_AF)
2295 vm_page_aflag_set(m, PGA_REFERENCED);
2296 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2297 pmap_pvh_free(&m->md, pmap, va);
2298 if (TAILQ_EMPTY(&m->md.pv_list) &&
2299 (m->flags & PG_FICTITIOUS) == 0) {
2300 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2301 if (TAILQ_EMPTY(&pvh->pv_list))
2302 vm_page_aflag_clear(m, PGA_WRITEABLE);
2305 return (pmap_unuse_pt(pmap, va, l2e, free));
2309 * Remove the given range of addresses from the specified map.
2311 * It is assumed that the start and end are properly
2312 * rounded to the page size.
2315 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2317 struct rwlock *lock;
2318 vm_offset_t va, va_next;
2319 pd_entry_t *l0, *l1, *l2;
2320 pt_entry_t l3_paddr, *l3;
2321 struct spglist free;
2324 * Perform an unsynchronized read. This is, however, safe.
2326 if (pmap->pm_stats.resident_count == 0)
2334 for (; sva < eva; sva = va_next) {
2336 if (pmap->pm_stats.resident_count == 0)
2339 l0 = pmap_l0(pmap, sva);
2340 if (pmap_load(l0) == 0) {
2341 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2347 l1 = pmap_l0_to_l1(l0, sva);
2348 if (pmap_load(l1) == 0) {
2349 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2356 * Calculate index for next page table.
2358 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2362 l2 = pmap_l1_to_l2(l1, sva);
2366 l3_paddr = pmap_load(l2);
2368 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2369 if (sva + L2_SIZE == va_next && eva >= va_next) {
2370 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2373 } else if (pmap_demote_l2_locked(pmap, l2,
2374 sva &~L2_OFFSET, &lock) == NULL)
2376 l3_paddr = pmap_load(l2);
2380 * Weed out invalid mappings.
2382 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2386 * Limit our scan to either the end of the va represented
2387 * by the current page table page, or to the end of the
2388 * range being removed.
2394 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2397 panic("l3 == NULL");
2398 if (pmap_load(l3) == 0) {
2399 if (va != va_next) {
2400 pmap_invalidate_range(pmap, va, sva);
2407 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2414 pmap_invalidate_range(pmap, va, sva);
2419 vm_page_free_pages_toq(&free, false);
2423 * Routine: pmap_remove_all
2425 * Removes this physical page from
2426 * all physical maps in which it resides.
2427 * Reflects back modify bits to the pager.
2430 * Original versions of this routine were very
2431 * inefficient because they iteratively called
2432 * pmap_remove (slow...)
2436 pmap_remove_all(vm_page_t m)
2438 struct md_page *pvh;
2441 struct rwlock *lock;
2442 pd_entry_t *pde, tpde;
2443 pt_entry_t *pte, tpte;
2445 struct spglist free;
2446 int lvl, pvh_gen, md_gen;
2448 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2449 ("pmap_remove_all: page %p is not managed", m));
2451 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2452 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2453 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2456 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2458 if (!PMAP_TRYLOCK(pmap)) {
2459 pvh_gen = pvh->pv_gen;
2463 if (pvh_gen != pvh->pv_gen) {
2470 pte = pmap_pte(pmap, va, &lvl);
2471 KASSERT(pte != NULL,
2472 ("pmap_remove_all: no page table entry found"));
2474 ("pmap_remove_all: invalid pte level %d", lvl));
2476 pmap_demote_l2_locked(pmap, pte, va, &lock);
2479 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2481 if (!PMAP_TRYLOCK(pmap)) {
2482 pvh_gen = pvh->pv_gen;
2483 md_gen = m->md.pv_gen;
2487 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2493 pmap_resident_count_dec(pmap, 1);
2495 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2496 KASSERT(pde != NULL,
2497 ("pmap_remove_all: no page directory entry found"));
2499 ("pmap_remove_all: invalid pde level %d", lvl));
2500 tpde = pmap_load(pde);
2502 pte = pmap_l2_to_l3(pde, pv->pv_va);
2503 tpte = pmap_load(pte);
2504 pmap_load_clear(pte);
2505 pmap_invalidate_page(pmap, pv->pv_va);
2506 if (tpte & ATTR_SW_WIRED)
2507 pmap->pm_stats.wired_count--;
2508 if ((tpte & ATTR_AF) != 0)
2509 vm_page_aflag_set(m, PGA_REFERENCED);
2512 * Update the vm_page_t clean and reference bits.
2514 if (pmap_page_dirty(tpte))
2516 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2517 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2519 free_pv_entry(pmap, pv);
2522 vm_page_aflag_clear(m, PGA_WRITEABLE);
2524 vm_page_free_pages_toq(&free, false);
2528 * Set the physical protection on the
2529 * specified range of this map as requested.
2532 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2534 vm_offset_t va, va_next;
2535 pd_entry_t *l0, *l1, *l2;
2536 pt_entry_t *l3p, l3, nbits;
2538 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2539 if (prot == VM_PROT_NONE) {
2540 pmap_remove(pmap, sva, eva);
2544 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2545 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2549 for (; sva < eva; sva = va_next) {
2551 l0 = pmap_l0(pmap, sva);
2552 if (pmap_load(l0) == 0) {
2553 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2559 l1 = pmap_l0_to_l1(l0, sva);
2560 if (pmap_load(l1) == 0) {
2561 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2567 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2571 l2 = pmap_l1_to_l2(l1, sva);
2572 if (pmap_load(l2) == 0)
2575 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2576 l3p = pmap_demote_l2(pmap, l2, sva);
2580 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2581 ("pmap_protect: Invalid L2 entry after demotion"));
2587 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2589 l3 = pmap_load(l3p);
2590 if (!pmap_l3_valid(l3))
2594 if ((prot & VM_PROT_WRITE) == 0) {
2595 if ((l3 & ATTR_SW_MANAGED) &&
2596 pmap_page_dirty(l3)) {
2597 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2600 nbits |= ATTR_AP(ATTR_AP_RO);
2602 if ((prot & VM_PROT_EXECUTE) == 0)
2605 pmap_set(l3p, nbits);
2606 /* XXX: Use pmap_invalidate_range */
2607 pmap_invalidate_page(pmap, sva);
2614 * Inserts the specified page table page into the specified pmap's collection
2615 * of idle page table pages. Each of a pmap's page table pages is responsible
2616 * for mapping a distinct range of virtual addresses. The pmap's collection is
2617 * ordered by this virtual address range.
2620 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2623 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2624 return (vm_radix_insert(&pmap->pm_root, mpte));
2628 * Removes the page table page mapping the specified virtual address from the
2629 * specified pmap's collection of idle page table pages, and returns it.
2630 * Otherwise, returns NULL if there is no page table page corresponding to the
2631 * specified virtual address.
2633 static __inline vm_page_t
2634 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2637 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2638 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2642 * Performs a break-before-make update of a pmap entry. This is needed when
2643 * either promoting or demoting pages to ensure the TLB doesn't get into an
2644 * inconsistent state.
2647 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2648 vm_offset_t va, vm_size_t size)
2652 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2655 * Ensure we don't get switched out with the page table in an
2656 * inconsistent state. We also need to ensure no interrupts fire
2657 * as they may make use of an address we are about to invalidate.
2659 intr = intr_disable();
2662 /* Clear the old mapping */
2663 pmap_load_clear(pte);
2664 pmap_invalidate_range_nopin(pmap, va, va + size);
2666 /* Create the new mapping */
2667 pmap_load_store(pte, newpte);
2673 #if VM_NRESERVLEVEL > 0
2675 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2676 * replace the many pv entries for the 4KB page mappings by a single pv entry
2677 * for the 2MB page mapping.
2680 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2681 struct rwlock **lockp)
2683 struct md_page *pvh;
2685 vm_offset_t va_last;
2688 KASSERT((pa & L2_OFFSET) == 0,
2689 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2690 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2693 * Transfer the first page's pv entry for this mapping to the 2mpage's
2694 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2695 * a transfer avoids the possibility that get_pv_entry() calls
2696 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2697 * mappings that is being promoted.
2699 m = PHYS_TO_VM_PAGE(pa);
2700 va = va & ~L2_OFFSET;
2701 pv = pmap_pvh_remove(&m->md, pmap, va);
2702 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2703 pvh = pa_to_pvh(pa);
2704 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2706 /* Free the remaining NPTEPG - 1 pv entries. */
2707 va_last = va + L2_SIZE - PAGE_SIZE;
2711 pmap_pvh_free(&m->md, pmap, va);
2712 } while (va < va_last);
2716 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2717 * single level 2 table entry to a single 2MB page mapping. For promotion
2718 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2719 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2720 * identical characteristics.
2723 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2724 struct rwlock **lockp)
2726 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2730 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2732 sva = va & ~L2_OFFSET;
2733 firstl3 = pmap_l2_to_l3(l2, sva);
2734 newl2 = pmap_load(firstl3);
2736 /* Check the alingment is valid */
2737 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2738 atomic_add_long(&pmap_l2_p_failures, 1);
2739 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2740 " in pmap %p", va, pmap);
2744 pa = newl2 + L2_SIZE - PAGE_SIZE;
2745 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2746 oldl3 = pmap_load(l3);
2748 atomic_add_long(&pmap_l2_p_failures, 1);
2749 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2750 " in pmap %p", va, pmap);
2757 * Save the page table page in its current state until the L2
2758 * mapping the superpage is demoted by pmap_demote_l2() or
2759 * destroyed by pmap_remove_l3().
2761 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2762 KASSERT(mpte >= vm_page_array &&
2763 mpte < &vm_page_array[vm_page_array_size],
2764 ("pmap_promote_l2: page table page is out of range"));
2765 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2766 ("pmap_promote_l2: page table page's pindex is wrong"));
2767 if (pmap_insert_pt_page(pmap, mpte)) {
2768 atomic_add_long(&pmap_l2_p_failures, 1);
2770 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2775 if ((newl2 & ATTR_SW_MANAGED) != 0)
2776 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2778 newl2 &= ~ATTR_DESCR_MASK;
2781 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2783 atomic_add_long(&pmap_l2_promotions, 1);
2784 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2787 #endif /* VM_NRESERVLEVEL > 0 */
2790 * Insert the given physical page (p) at
2791 * the specified virtual address (v) in the
2792 * target physical map with the protection requested.
2794 * If specified, the page will be wired down, meaning
2795 * that the related pte can not be reclaimed.
2797 * NB: This is the only routine which MAY NOT lazy-evaluate
2798 * or lose information. That is, this routine must actually
2799 * insert this page into the given map NOW.
2802 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2803 u_int flags, int8_t psind __unused)
2805 struct rwlock *lock;
2807 pt_entry_t new_l3, orig_l3;
2808 pt_entry_t *l2, *l3;
2810 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2811 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2815 va = trunc_page(va);
2816 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2817 VM_OBJECT_ASSERT_LOCKED(m->object);
2818 pa = VM_PAGE_TO_PHYS(m);
2819 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2821 if ((prot & VM_PROT_WRITE) == 0)
2822 new_l3 |= ATTR_AP(ATTR_AP_RO);
2823 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2825 if ((flags & PMAP_ENTER_WIRED) != 0)
2826 new_l3 |= ATTR_SW_WIRED;
2827 if (va < VM_MAXUSER_ADDRESS)
2828 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2830 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2837 pde = pmap_pde(pmap, va, &lvl);
2838 if (pde != NULL && lvl == 1) {
2839 l2 = pmap_l1_to_l2(pde, va);
2840 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
2841 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
2843 l3 = &l3[pmap_l3_index(va)];
2844 if (va < VM_MAXUSER_ADDRESS) {
2845 mpte = PHYS_TO_VM_PAGE(
2846 pmap_load(l2) & ~ATTR_MASK);
2853 if (va < VM_MAXUSER_ADDRESS) {
2854 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2855 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2856 if (mpte == NULL && nosleep) {
2857 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2861 return (KERN_RESOURCE_SHORTAGE);
2863 pde = pmap_pde(pmap, va, &lvl);
2864 KASSERT(pde != NULL,
2865 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2867 ("pmap_enter: Invalid level %d", lvl));
2870 * If we get a level 2 pde it must point to a level 3 entry
2871 * otherwise we will need to create the intermediate tables
2877 /* Get the l0 pde to update */
2878 pde = pmap_l0(pmap, va);
2879 KASSERT(pde != NULL, ("..."));
2881 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2882 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2885 panic("pmap_enter: l1 pte_m == NULL");
2886 if ((l1_m->flags & PG_ZERO) == 0)
2887 pmap_zero_page(l1_m);
2889 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2890 pmap_load_store(pde, l1_pa | L0_TABLE);
2893 /* Get the l1 pde to update */
2894 pde = pmap_l1_to_l2(pde, va);
2895 KASSERT(pde != NULL, ("..."));
2897 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2898 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2901 panic("pmap_enter: l2 pte_m == NULL");
2902 if ((l2_m->flags & PG_ZERO) == 0)
2903 pmap_zero_page(l2_m);
2905 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2906 pmap_load_store(pde, l2_pa | L1_TABLE);
2909 /* Get the l2 pde to update */
2910 pde = pmap_l1_to_l2(pde, va);
2911 KASSERT(pde != NULL, ("..."));
2913 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2914 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2917 panic("pmap_enter: l3 pte_m == NULL");
2918 if ((l3_m->flags & PG_ZERO) == 0)
2919 pmap_zero_page(l3_m);
2921 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2922 pmap_load_store(pde, l3_pa | L2_TABLE);
2927 l3 = pmap_l2_to_l3(pde, va);
2931 orig_l3 = pmap_load(l3);
2932 opa = orig_l3 & ~ATTR_MASK;
2935 * Is the specified virtual address already mapped?
2937 if (pmap_l3_valid(orig_l3)) {
2939 * Wiring change, just update stats. We don't worry about
2940 * wiring PT pages as they remain resident as long as there
2941 * are valid mappings in them. Hence, if a user page is wired,
2942 * the PT page will be also.
2944 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2945 (orig_l3 & ATTR_SW_WIRED) == 0)
2946 pmap->pm_stats.wired_count++;
2947 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2948 (orig_l3 & ATTR_SW_WIRED) != 0)
2949 pmap->pm_stats.wired_count--;
2952 * Remove the extra PT page reference.
2956 KASSERT(mpte->wire_count > 0,
2957 ("pmap_enter: missing reference to page table page,"
2962 * Has the physical page changed?
2966 * No, might be a protection or wiring change.
2968 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2969 new_l3 |= ATTR_SW_MANAGED;
2970 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2971 ATTR_AP(ATTR_AP_RW)) {
2972 vm_page_aflag_set(m, PGA_WRITEABLE);
2979 * Increment the counters.
2981 if ((new_l3 & ATTR_SW_WIRED) != 0)
2982 pmap->pm_stats.wired_count++;
2983 pmap_resident_count_inc(pmap, 1);
2986 * Enter on the PV list if part of our managed memory.
2988 if ((m->oflags & VPO_UNMANAGED) == 0) {
2989 new_l3 |= ATTR_SW_MANAGED;
2990 pv = get_pv_entry(pmap, &lock);
2992 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
2993 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2995 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2996 vm_page_aflag_set(m, PGA_WRITEABLE);
3001 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3002 * is set. Do it now, before the mapping is stored and made
3003 * valid for hardware table walk. If done later, then other can
3004 * access this page before caches are properly synced.
3005 * Don't do it for kernel memory which is mapped with exec
3006 * permission even if the memory isn't going to hold executable
3007 * code. The only time when icache sync is needed is after
3008 * kernel module is loaded and the relocation info is processed.
3009 * And it's done in elf_cpu_load_file().
3011 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3012 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3013 (opa != pa || (orig_l3 & ATTR_XN)))
3014 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3017 * Update the L3 entry
3019 if (pmap_l3_valid(orig_l3)) {
3022 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE);
3023 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3024 om = PHYS_TO_VM_PAGE(opa);
3025 if (pmap_page_dirty(orig_l3))
3027 if ((orig_l3 & ATTR_AF) != 0)
3028 vm_page_aflag_set(om, PGA_REFERENCED);
3029 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3030 pmap_pvh_free(&om->md, pmap, va);
3031 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3032 TAILQ_EMPTY(&om->md.pv_list) &&
3033 ((om->flags & PG_FICTITIOUS) != 0 ||
3034 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3035 vm_page_aflag_clear(om, PGA_WRITEABLE);
3037 } else if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3038 /* same PA, different attributes */
3039 pmap_load_store(l3, new_l3);
3040 pmap_invalidate_page(pmap, va);
3041 if (pmap_page_dirty(orig_l3) &&
3042 (orig_l3 & ATTR_SW_MANAGED) != 0)
3047 * This can happens if multiple threads simultaneously
3048 * access not yet mapped page. This bad for performance
3049 * since this can cause full demotion-NOP-promotion
3051 * Another possible reasons are:
3052 * - VM and pmap memory layout are diverged
3053 * - tlb flush is missing somewhere and CPU doesn't see
3056 CTR4(KTR_PMAP, "%s: already mapped page - "
3057 "pmap %p va 0x%#lx pte 0x%lx",
3058 __func__, pmap, va, new_l3);
3062 pmap_load_store(l3, new_l3);
3065 #if VM_NRESERVLEVEL > 0
3066 if (pmap != pmap_kernel() &&
3067 (mpte == NULL || mpte->wire_count == NL3PG) &&
3068 pmap_superpages_enabled() &&
3069 (m->flags & PG_FICTITIOUS) == 0 &&
3070 vm_reserv_level_iffullpop(m) == 0) {
3071 pmap_promote_l2(pmap, pde, va, &lock);
3078 return (KERN_SUCCESS);
3082 * Maps a sequence of resident pages belonging to the same object.
3083 * The sequence begins with the given page m_start. This page is
3084 * mapped at the given virtual address start. Each subsequent page is
3085 * mapped at a virtual address that is offset from start by the same
3086 * amount as the page is offset from m_start within the object. The
3087 * last page in the sequence is the page with the largest offset from
3088 * m_start that can be mapped at a virtual address less than the given
3089 * virtual address end. Not every virtual page between start and end
3090 * is mapped; only those for which a resident page exists with the
3091 * corresponding offset from m_start are mapped.
3094 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3095 vm_page_t m_start, vm_prot_t prot)
3097 struct rwlock *lock;
3100 vm_pindex_t diff, psize;
3102 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3104 psize = atop(end - start);
3109 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3110 va = start + ptoa(diff);
3111 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
3112 m = TAILQ_NEXT(m, listq);
3120 * this code makes some *MAJOR* assumptions:
3121 * 1. Current pmap & pmap exists.
3124 * 4. No page table pages.
3125 * but is *MUCH* faster than pmap_enter...
3129 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3131 struct rwlock *lock;
3135 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3142 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3143 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3145 struct spglist free;
3147 pt_entry_t *l2, *l3, l3_val;
3151 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3152 (m->oflags & VPO_UNMANAGED) != 0,
3153 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3154 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3156 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3158 * In the case that a page table page is not
3159 * resident, we are creating it here.
3161 if (va < VM_MAXUSER_ADDRESS) {
3162 vm_pindex_t l2pindex;
3165 * Calculate pagetable page index
3167 l2pindex = pmap_l2_pindex(va);
3168 if (mpte && (mpte->pindex == l2pindex)) {
3174 pde = pmap_pde(pmap, va, &lvl);
3177 * If the page table page is mapped, we just increment
3178 * the hold count, and activate it. Otherwise, we
3179 * attempt to allocate a page table page. If this
3180 * attempt fails, we don't retry. Instead, we give up.
3183 l2 = pmap_l1_to_l2(pde, va);
3184 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3188 if (lvl == 2 && pmap_load(pde) != 0) {
3190 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3194 * Pass NULL instead of the PV list lock
3195 * pointer, because we don't intend to sleep.
3197 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3202 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3203 l3 = &l3[pmap_l3_index(va)];
3206 pde = pmap_pde(kernel_pmap, va, &lvl);
3207 KASSERT(pde != NULL,
3208 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3211 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3212 l3 = pmap_l2_to_l3(pde, va);
3215 if (pmap_load(l3) != 0) {
3224 * Enter on the PV list if part of our managed memory.
3226 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3227 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3230 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3231 pmap_invalidate_page(pmap, va);
3232 vm_page_free_pages_toq(&free, false);
3240 * Increment counters
3242 pmap_resident_count_inc(pmap, 1);
3244 pa = VM_PAGE_TO_PHYS(m);
3245 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3246 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3247 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3249 else if (va < VM_MAXUSER_ADDRESS)
3253 * Now validate mapping with RO protection
3255 if ((m->oflags & VPO_UNMANAGED) == 0)
3256 l3_val |= ATTR_SW_MANAGED;
3258 /* Sync icache before the mapping is stored to PTE */
3259 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3260 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3261 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3263 pmap_load_store(l3, l3_val);
3264 pmap_invalidate_page(pmap, va);
3269 * This code maps large physical mmap regions into the
3270 * processor address space. Note that some shortcuts
3271 * are taken, but the code works.
3274 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3275 vm_pindex_t pindex, vm_size_t size)
3278 VM_OBJECT_ASSERT_WLOCKED(object);
3279 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3280 ("pmap_object_init_pt: non-device object"));
3284 * Clear the wired attribute from the mappings for the specified range of
3285 * addresses in the given pmap. Every valid mapping within that range
3286 * must have the wired attribute set. In contrast, invalid mappings
3287 * cannot have the wired attribute set, so they are ignored.
3289 * The wired attribute of the page table entry is not a hardware feature,
3290 * so there is no need to invalidate any TLB entries.
3293 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3295 vm_offset_t va_next;
3296 pd_entry_t *l0, *l1, *l2;
3300 for (; sva < eva; sva = va_next) {
3301 l0 = pmap_l0(pmap, sva);
3302 if (pmap_load(l0) == 0) {
3303 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3309 l1 = pmap_l0_to_l1(l0, sva);
3310 if (pmap_load(l1) == 0) {
3311 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3317 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3321 l2 = pmap_l1_to_l2(l1, sva);
3322 if (pmap_load(l2) == 0)
3325 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3326 l3 = pmap_demote_l2(pmap, l2, sva);
3330 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3331 ("pmap_unwire: Invalid l2 entry after demotion"));
3335 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3337 if (pmap_load(l3) == 0)
3339 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3340 panic("pmap_unwire: l3 %#jx is missing "
3341 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3344 * PG_W must be cleared atomically. Although the pmap
3345 * lock synchronizes access to PG_W, another processor
3346 * could be setting PG_M and/or PG_A concurrently.
3348 atomic_clear_long(l3, ATTR_SW_WIRED);
3349 pmap->pm_stats.wired_count--;
3356 * Copy the range specified by src_addr/len
3357 * from the source map to the range dst_addr/len
3358 * in the destination map.
3360 * This routine is only advisory and need not do anything.
3364 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3365 vm_offset_t src_addr)
3370 * pmap_zero_page zeros the specified hardware page by mapping
3371 * the page into KVM and using bzero to clear its contents.
3374 pmap_zero_page(vm_page_t m)
3376 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3378 pagezero((void *)va);
3382 * pmap_zero_page_area zeros the specified hardware page by mapping
3383 * the page into KVM and using bzero to clear its contents.
3385 * off and size may not cover an area beyond a single hardware page.
3388 pmap_zero_page_area(vm_page_t m, int off, int size)
3390 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3392 if (off == 0 && size == PAGE_SIZE)
3393 pagezero((void *)va);
3395 bzero((char *)va + off, size);
3399 * pmap_copy_page copies the specified (machine independent)
3400 * page by mapping the page into virtual memory and using
3401 * bcopy to copy the page, one machine dependent page at a
3405 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3407 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3408 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3410 pagecopy((void *)src, (void *)dst);
3413 int unmapped_buf_allowed = 1;
3416 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3417 vm_offset_t b_offset, int xfersize)
3421 vm_paddr_t p_a, p_b;
3422 vm_offset_t a_pg_offset, b_pg_offset;
3425 while (xfersize > 0) {
3426 a_pg_offset = a_offset & PAGE_MASK;
3427 m_a = ma[a_offset >> PAGE_SHIFT];
3428 p_a = m_a->phys_addr;
3429 b_pg_offset = b_offset & PAGE_MASK;
3430 m_b = mb[b_offset >> PAGE_SHIFT];
3431 p_b = m_b->phys_addr;
3432 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3433 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3434 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3435 panic("!DMAP a %lx", p_a);
3437 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3439 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3440 panic("!DMAP b %lx", p_b);
3442 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3444 bcopy(a_cp, b_cp, cnt);
3452 pmap_quick_enter_page(vm_page_t m)
3455 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3459 pmap_quick_remove_page(vm_offset_t addr)
3464 * Returns true if the pmap's pv is one of the first
3465 * 16 pvs linked to from this page. This count may
3466 * be changed upwards or downwards in the future; it
3467 * is only necessary that true be returned for a small
3468 * subset of pmaps for proper page aging.
3471 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3473 struct md_page *pvh;
3474 struct rwlock *lock;
3479 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3480 ("pmap_page_exists_quick: page %p is not managed", m));
3482 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3484 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3485 if (PV_PMAP(pv) == pmap) {
3493 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3494 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3495 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3496 if (PV_PMAP(pv) == pmap) {
3510 * pmap_page_wired_mappings:
3512 * Return the number of managed mappings to the given physical page
3516 pmap_page_wired_mappings(vm_page_t m)
3518 struct rwlock *lock;
3519 struct md_page *pvh;
3523 int count, lvl, md_gen, pvh_gen;
3525 if ((m->oflags & VPO_UNMANAGED) != 0)
3527 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3531 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3533 if (!PMAP_TRYLOCK(pmap)) {
3534 md_gen = m->md.pv_gen;
3538 if (md_gen != m->md.pv_gen) {
3543 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3544 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3548 if ((m->flags & PG_FICTITIOUS) == 0) {
3549 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3550 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3552 if (!PMAP_TRYLOCK(pmap)) {
3553 md_gen = m->md.pv_gen;
3554 pvh_gen = pvh->pv_gen;
3558 if (md_gen != m->md.pv_gen ||
3559 pvh_gen != pvh->pv_gen) {
3564 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3566 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3576 * Destroy all managed, non-wired mappings in the given user-space
3577 * pmap. This pmap cannot be active on any processor besides the
3580 * This function cannot be applied to the kernel pmap. Moreover, it
3581 * is not intended for general use. It is only to be used during
3582 * process termination. Consequently, it can be implemented in ways
3583 * that make it faster than pmap_remove(). First, it can more quickly
3584 * destroy mappings by iterating over the pmap's collection of PV
3585 * entries, rather than searching the page table. Second, it doesn't
3586 * have to test and clear the page table entries atomically, because
3587 * no processor is currently accessing the user address space. In
3588 * particular, a page table entry's dirty bit won't change state once
3589 * this function starts.
3592 pmap_remove_pages(pmap_t pmap)
3595 pt_entry_t *pte, tpte;
3596 struct spglist free;
3597 vm_page_t m, ml3, mt;
3599 struct md_page *pvh;
3600 struct pv_chunk *pc, *npc;
3601 struct rwlock *lock;
3603 uint64_t inuse, bitmask;
3604 int allfree, field, freed, idx, lvl;
3611 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3614 for (field = 0; field < _NPCM; field++) {
3615 inuse = ~pc->pc_map[field] & pc_freemask[field];
3616 while (inuse != 0) {
3617 bit = ffsl(inuse) - 1;
3618 bitmask = 1UL << bit;
3619 idx = field * 64 + bit;
3620 pv = &pc->pc_pventry[idx];
3623 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3624 KASSERT(pde != NULL,
3625 ("Attempting to remove an unmapped page"));
3629 pte = pmap_l1_to_l2(pde, pv->pv_va);
3630 tpte = pmap_load(pte);
3631 KASSERT((tpte & ATTR_DESCR_MASK) ==
3633 ("Attempting to remove an invalid "
3634 "block: %lx", tpte));
3635 tpte = pmap_load(pte);
3638 pte = pmap_l2_to_l3(pde, pv->pv_va);
3639 tpte = pmap_load(pte);
3640 KASSERT((tpte & ATTR_DESCR_MASK) ==
3642 ("Attempting to remove an invalid "
3643 "page: %lx", tpte));
3647 "Invalid page directory level: %d",
3652 * We cannot remove wired pages from a process' mapping at this time
3654 if (tpte & ATTR_SW_WIRED) {
3659 pa = tpte & ~ATTR_MASK;
3661 m = PHYS_TO_VM_PAGE(pa);
3662 KASSERT(m->phys_addr == pa,
3663 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3664 m, (uintmax_t)m->phys_addr,
3667 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
3668 m < &vm_page_array[vm_page_array_size],
3669 ("pmap_remove_pages: bad pte %#jx",
3672 pmap_load_clear(pte);
3675 * Update the vm_page_t clean/reference bits.
3677 if ((tpte & ATTR_AP_RW_BIT) ==
3678 ATTR_AP(ATTR_AP_RW)) {
3681 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3690 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
3693 pc->pc_map[field] |= bitmask;
3696 pmap_resident_count_dec(pmap,
3697 L2_SIZE / PAGE_SIZE);
3698 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
3699 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
3701 if (TAILQ_EMPTY(&pvh->pv_list)) {
3702 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3703 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
3704 TAILQ_EMPTY(&mt->md.pv_list))
3705 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3707 ml3 = pmap_remove_pt_page(pmap,
3710 pmap_resident_count_dec(pmap,1);
3711 KASSERT(ml3->wire_count == NL3PG,
3712 ("pmap_remove_pages: l3 page wire count error"));
3713 ml3->wire_count = 1;
3714 vm_page_unwire_noq(ml3);
3715 pmap_add_delayed_free_list(ml3,
3720 pmap_resident_count_dec(pmap, 1);
3721 TAILQ_REMOVE(&m->md.pv_list, pv,
3724 if ((m->aflags & PGA_WRITEABLE) != 0 &&
3725 TAILQ_EMPTY(&m->md.pv_list) &&
3726 (m->flags & PG_FICTITIOUS) == 0) {
3728 VM_PAGE_TO_PHYS(m));
3729 if (TAILQ_EMPTY(&pvh->pv_list))
3730 vm_page_aflag_clear(m,
3735 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
3740 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3741 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3742 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3744 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3748 pmap_invalidate_all(pmap);
3752 vm_page_free_pages_toq(&free, false);
3756 * This is used to check if a page has been accessed or modified. As we
3757 * don't have a bit to see if it has been modified we have to assume it
3758 * has been if the page is read/write.
3761 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3763 struct rwlock *lock;
3765 struct md_page *pvh;
3766 pt_entry_t *pte, mask, value;
3768 int lvl, md_gen, pvh_gen;
3772 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3775 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3777 if (!PMAP_TRYLOCK(pmap)) {
3778 md_gen = m->md.pv_gen;
3782 if (md_gen != m->md.pv_gen) {
3787 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3789 ("pmap_page_test_mappings: Invalid level %d", lvl));
3793 mask |= ATTR_AP_RW_BIT;
3794 value |= ATTR_AP(ATTR_AP_RW);
3797 mask |= ATTR_AF | ATTR_DESCR_MASK;
3798 value |= ATTR_AF | L3_PAGE;
3800 rv = (pmap_load(pte) & mask) == value;
3805 if ((m->flags & PG_FICTITIOUS) == 0) {
3806 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3807 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3809 if (!PMAP_TRYLOCK(pmap)) {
3810 md_gen = m->md.pv_gen;
3811 pvh_gen = pvh->pv_gen;
3815 if (md_gen != m->md.pv_gen ||
3816 pvh_gen != pvh->pv_gen) {
3821 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3823 ("pmap_page_test_mappings: Invalid level %d", lvl));
3827 mask |= ATTR_AP_RW_BIT;
3828 value |= ATTR_AP(ATTR_AP_RW);
3831 mask |= ATTR_AF | ATTR_DESCR_MASK;
3832 value |= ATTR_AF | L2_BLOCK;
3834 rv = (pmap_load(pte) & mask) == value;
3848 * Return whether or not the specified physical page was modified
3849 * in any physical maps.
3852 pmap_is_modified(vm_page_t m)
3855 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3856 ("pmap_is_modified: page %p is not managed", m));
3859 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3860 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3861 * is clear, no PTEs can have PG_M set.
3863 VM_OBJECT_ASSERT_WLOCKED(m->object);
3864 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3866 return (pmap_page_test_mappings(m, FALSE, TRUE));
3870 * pmap_is_prefaultable:
3872 * Return whether or not the specified virtual address is eligible
3876 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3884 pte = pmap_pte(pmap, addr, &lvl);
3885 if (pte != NULL && pmap_load(pte) != 0) {
3893 * pmap_is_referenced:
3895 * Return whether or not the specified physical page was referenced
3896 * in any physical maps.
3899 pmap_is_referenced(vm_page_t m)
3902 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3903 ("pmap_is_referenced: page %p is not managed", m));
3904 return (pmap_page_test_mappings(m, TRUE, FALSE));
3908 * Clear the write and modified bits in each of the given page's mappings.
3911 pmap_remove_write(vm_page_t m)
3913 struct md_page *pvh;
3915 struct rwlock *lock;
3916 pv_entry_t next_pv, pv;
3917 pt_entry_t oldpte, *pte;
3919 int lvl, md_gen, pvh_gen;
3921 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3922 ("pmap_remove_write: page %p is not managed", m));
3925 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3926 * set by another thread while the object is locked. Thus,
3927 * if PGA_WRITEABLE is clear, no page table entries need updating.
3929 VM_OBJECT_ASSERT_WLOCKED(m->object);
3930 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3932 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3933 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3934 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3937 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
3939 if (!PMAP_TRYLOCK(pmap)) {
3940 pvh_gen = pvh->pv_gen;
3944 if (pvh_gen != pvh->pv_gen) {
3951 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3952 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3953 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
3955 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3956 ("inconsistent pv lock %p %p for page %p",
3957 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3960 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3962 if (!PMAP_TRYLOCK(pmap)) {
3963 pvh_gen = pvh->pv_gen;
3964 md_gen = m->md.pv_gen;
3968 if (pvh_gen != pvh->pv_gen ||
3969 md_gen != m->md.pv_gen) {
3975 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3977 oldpte = pmap_load(pte);
3978 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3979 if (!atomic_cmpset_long(pte, oldpte,
3980 oldpte | ATTR_AP(ATTR_AP_RO)))
3982 if ((oldpte & ATTR_AF) != 0)
3984 pmap_invalidate_page(pmap, pv->pv_va);
3989 vm_page_aflag_clear(m, PGA_WRITEABLE);
3992 static __inline boolean_t
3993 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
4000 * pmap_ts_referenced:
4002 * Return a count of reference bits for a page, clearing those bits.
4003 * It is not necessary for every reference bit to be cleared, but it
4004 * is necessary that 0 only be returned when there are truly no
4005 * reference bits set.
4007 * As an optimization, update the page's dirty field if a modified bit is
4008 * found while counting reference bits. This opportunistic update can be
4009 * performed at low cost and can eliminate the need for some future calls
4010 * to pmap_is_modified(). However, since this function stops after
4011 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4012 * dirty pages. Those dirty pages will only be detected by a future call
4013 * to pmap_is_modified().
4016 pmap_ts_referenced(vm_page_t m)
4018 struct md_page *pvh;
4021 struct rwlock *lock;
4022 pd_entry_t *pde, tpde;
4023 pt_entry_t *pte, tpte;
4027 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4028 struct spglist free;
4031 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4032 ("pmap_ts_referenced: page %p is not managed", m));
4035 pa = VM_PAGE_TO_PHYS(m);
4036 lock = PHYS_TO_PV_LIST_LOCK(pa);
4037 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4041 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4042 goto small_mappings;
4048 if (!PMAP_TRYLOCK(pmap)) {
4049 pvh_gen = pvh->pv_gen;
4053 if (pvh_gen != pvh->pv_gen) {
4059 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4060 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4062 ("pmap_ts_referenced: invalid pde level %d", lvl));
4063 tpde = pmap_load(pde);
4064 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4065 ("pmap_ts_referenced: found an invalid l1 table"));
4066 pte = pmap_l1_to_l2(pde, pv->pv_va);
4067 tpte = pmap_load(pte);
4068 if (pmap_page_dirty(tpte)) {
4070 * Although "tpte" is mapping a 2MB page, because
4071 * this function is called at a 4KB page granularity,
4072 * we only update the 4KB page under test.
4076 if ((tpte & ATTR_AF) != 0) {
4078 * Since this reference bit is shared by 512 4KB
4079 * pages, it should not be cleared every time it is
4080 * tested. Apply a simple "hash" function on the
4081 * physical page number, the virtual superpage number,
4082 * and the pmap address to select one 4KB page out of
4083 * the 512 on which testing the reference bit will
4084 * result in clearing that reference bit. This
4085 * function is designed to avoid the selection of the
4086 * same 4KB page for every 2MB page mapping.
4088 * On demotion, a mapping that hasn't been referenced
4089 * is simply destroyed. To avoid the possibility of a
4090 * subsequent page fault on a demoted wired mapping,
4091 * always leave its reference bit set. Moreover,
4092 * since the superpage is wired, the current state of
4093 * its reference bit won't affect page replacement.
4095 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4096 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4097 (tpte & ATTR_SW_WIRED) == 0) {
4098 if (safe_to_clear_referenced(pmap, tpte)) {
4100 * TODO: We don't handle the access
4101 * flag at all. We need to be able
4102 * to set it in the exception handler.
4105 "safe_to_clear_referenced\n");
4106 } else if (pmap_demote_l2_locked(pmap, pte,
4107 pv->pv_va, &lock) != NULL) {
4109 va += VM_PAGE_TO_PHYS(m) -
4110 (tpte & ~ATTR_MASK);
4111 l3 = pmap_l2_to_l3(pte, va);
4112 pmap_remove_l3(pmap, l3, va,
4113 pmap_load(pte), NULL, &lock);
4119 * The superpage mapping was removed
4120 * entirely and therefore 'pv' is no
4128 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4129 ("inconsistent pv lock %p %p for page %p",
4130 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4135 /* Rotate the PV list if it has more than one entry. */
4136 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4137 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4138 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4141 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4143 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4145 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4152 if (!PMAP_TRYLOCK(pmap)) {
4153 pvh_gen = pvh->pv_gen;
4154 md_gen = m->md.pv_gen;
4158 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4163 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4164 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4166 ("pmap_ts_referenced: invalid pde level %d", lvl));
4167 tpde = pmap_load(pde);
4168 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4169 ("pmap_ts_referenced: found an invalid l2 table"));
4170 pte = pmap_l2_to_l3(pde, pv->pv_va);
4171 tpte = pmap_load(pte);
4172 if (pmap_page_dirty(tpte))
4174 if ((tpte & ATTR_AF) != 0) {
4175 if (safe_to_clear_referenced(pmap, tpte)) {
4177 * TODO: We don't handle the access flag
4178 * at all. We need to be able to set it in
4179 * the exception handler.
4181 panic("ARM64TODO: safe_to_clear_referenced\n");
4182 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4184 * Wired pages cannot be paged out so
4185 * doing accessed bit emulation for
4186 * them is wasted effort. We do the
4187 * hard work for unwired pages only.
4189 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4191 pmap_invalidate_page(pmap, pv->pv_va);
4196 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4197 ("inconsistent pv lock %p %p for page %p",
4198 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4203 /* Rotate the PV list if it has more than one entry. */
4204 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4205 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4206 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4209 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4210 not_cleared < PMAP_TS_REFERENCED_MAX);
4213 vm_page_free_pages_toq(&free, false);
4214 return (cleared + not_cleared);
4218 * Apply the given advice to the specified range of addresses within the
4219 * given pmap. Depending on the advice, clear the referenced and/or
4220 * modified flags in each mapping and set the mapped page's dirty field.
4223 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4228 * Clear the modify bits on the specified physical page.
4231 pmap_clear_modify(vm_page_t m)
4234 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4235 ("pmap_clear_modify: page %p is not managed", m));
4236 VM_OBJECT_ASSERT_WLOCKED(m->object);
4237 KASSERT(!vm_page_xbusied(m),
4238 ("pmap_clear_modify: page %p is exclusive busied", m));
4241 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4242 * If the object containing the page is locked and the page is not
4243 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4245 if ((m->aflags & PGA_WRITEABLE) == 0)
4248 /* ARM64TODO: We lack support for tracking if a page is modified */
4252 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4255 return ((void *)PHYS_TO_DMAP(pa));
4259 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
4264 * Sets the memory attribute for the specified page.
4267 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4270 m->md.pv_memattr = ma;
4273 * If "m" is a normal page, update its direct mapping. This update
4274 * can be relied upon to perform any cache operations that are
4275 * required for data coherence.
4277 if ((m->flags & PG_FICTITIOUS) == 0 &&
4278 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4279 m->md.pv_memattr) != 0)
4280 panic("memory attribute change on the direct map failed");
4284 * Changes the specified virtual address range's memory type to that given by
4285 * the parameter "mode". The specified virtual address range must be
4286 * completely contained within either the direct map or the kernel map. If
4287 * the virtual address range is contained within the kernel map, then the
4288 * memory type for each of the corresponding ranges of the direct map is also
4289 * changed. (The corresponding ranges of the direct map are those ranges that
4290 * map the same physical pages as the specified virtual address range.) These
4291 * changes to the direct map are necessary because Intel describes the
4292 * behavior of their processors as "undefined" if two or more mappings to the
4293 * same physical page have different memory types.
4295 * Returns zero if the change completed successfully, and either EINVAL or
4296 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4297 * of the virtual address range was not mapped, and ENOMEM is returned if
4298 * there was insufficient memory available to complete the change. In the
4299 * latter case, the memory type may have been changed on some part of the
4300 * virtual address range or the direct map.
4303 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4307 PMAP_LOCK(kernel_pmap);
4308 error = pmap_change_attr_locked(va, size, mode);
4309 PMAP_UNLOCK(kernel_pmap);
4314 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4316 vm_offset_t base, offset, tmpva;
4317 pt_entry_t l3, *pte, *newpte;
4320 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4321 base = trunc_page(va);
4322 offset = va & PAGE_MASK;
4323 size = round_page(offset + size);
4325 if (!VIRT_IN_DMAP(base))
4328 for (tmpva = base; tmpva < base + size; ) {
4329 pte = pmap_pte(kernel_pmap, va, &lvl);
4333 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4335 * We already have the correct attribute,
4336 * ignore this entry.
4340 panic("Invalid DMAP table level: %d\n", lvl);
4342 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4345 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4353 * Split the entry to an level 3 table, then
4354 * set the new attribute.
4358 panic("Invalid DMAP table level: %d\n", lvl);
4360 newpte = pmap_demote_l1(kernel_pmap, pte,
4361 tmpva & ~L1_OFFSET);
4364 pte = pmap_l1_to_l2(pte, tmpva);
4366 newpte = pmap_demote_l2(kernel_pmap, pte,
4367 tmpva & ~L2_OFFSET);
4370 pte = pmap_l2_to_l3(pte, tmpva);
4372 /* Update the entry */
4373 l3 = pmap_load(pte);
4374 l3 &= ~ATTR_IDX_MASK;
4375 l3 |= ATTR_IDX(mode);
4376 if (mode == DEVICE_MEMORY)
4379 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4383 * If moving to a non-cacheable entry flush
4386 if (mode == VM_MEMATTR_UNCACHEABLE)
4387 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4399 * Create an L2 table to map all addresses within an L1 mapping.
4402 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4404 pt_entry_t *l2, newl2, oldl1;
4406 vm_paddr_t l2phys, phys;
4410 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4411 oldl1 = pmap_load(l1);
4412 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4413 ("pmap_demote_l1: Demoting a non-block entry"));
4414 KASSERT((va & L1_OFFSET) == 0,
4415 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4416 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4417 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4420 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4421 tmpl1 = kva_alloc(PAGE_SIZE);
4426 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4427 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4428 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4429 " in pmap %p", va, pmap);
4433 l2phys = VM_PAGE_TO_PHYS(ml2);
4434 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4436 /* Address the range points at */
4437 phys = oldl1 & ~ATTR_MASK;
4438 /* The attributed from the old l1 table to be copied */
4439 newl2 = oldl1 & ATTR_MASK;
4441 /* Create the new entries */
4442 for (i = 0; i < Ln_ENTRIES; i++) {
4443 l2[i] = newl2 | phys;
4446 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4447 ("Invalid l2 page (%lx != %lx)", l2[0],
4448 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4451 pmap_kenter(tmpl1, PAGE_SIZE,
4452 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4453 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4456 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4459 pmap_kremove(tmpl1);
4460 kva_free(tmpl1, PAGE_SIZE);
4467 * Create an L3 table to map all addresses within an L2 mapping.
4470 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4471 struct rwlock **lockp)
4473 pt_entry_t *l3, newl3, oldl2;
4475 vm_paddr_t l3phys, phys;
4479 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4481 oldl2 = pmap_load(l2);
4482 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4483 ("pmap_demote_l2: Demoting a non-block entry"));
4484 KASSERT((va & L2_OFFSET) == 0,
4485 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4488 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4489 tmpl2 = kva_alloc(PAGE_SIZE);
4494 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4495 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4496 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4497 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4499 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4500 " in pmap %p", va, pmap);
4503 if (va < VM_MAXUSER_ADDRESS)
4504 pmap_resident_count_inc(pmap, 1);
4507 l3phys = VM_PAGE_TO_PHYS(ml3);
4508 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4510 /* Address the range points at */
4511 phys = oldl2 & ~ATTR_MASK;
4512 /* The attributed from the old l2 table to be copied */
4513 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
4516 * If the page table page is new, initialize it.
4518 if (ml3->wire_count == 1) {
4519 for (i = 0; i < Ln_ENTRIES; i++) {
4520 l3[i] = newl3 | phys;
4524 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
4525 ("Invalid l3 page (%lx != %lx)", l3[0],
4526 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
4529 * Map the temporary page so we don't lose access to the l2 table.
4532 pmap_kenter(tmpl2, PAGE_SIZE,
4533 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
4534 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
4538 * The spare PV entries must be reserved prior to demoting the
4539 * mapping, that is, prior to changing the PDE. Otherwise, the state
4540 * of the L2 and the PV lists will be inconsistent, which can result
4541 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4542 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
4543 * PV entry for the 2MB page mapping that is being demoted.
4545 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4546 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
4548 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
4551 * Demote the PV entry.
4553 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4554 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
4556 atomic_add_long(&pmap_l2_demotions, 1);
4557 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
4558 " in pmap %p %lx", va, pmap, l3[0]);
4562 pmap_kremove(tmpl2);
4563 kva_free(tmpl2, PAGE_SIZE);
4571 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
4573 struct rwlock *lock;
4577 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
4584 * perform the pmap work for mincore
4587 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4589 pd_entry_t *l1p, l1;
4590 pd_entry_t *l2p, l2;
4591 pt_entry_t *l3p, l3;
4602 l1p = pmap_l1(pmap, addr);
4603 if (l1p == NULL) /* No l1 */
4606 l1 = pmap_load(l1p);
4607 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
4610 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
4611 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
4612 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4613 val = MINCORE_SUPER | MINCORE_INCORE;
4614 if (pmap_page_dirty(l1))
4615 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4616 if ((l1 & ATTR_AF) == ATTR_AF)
4617 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4621 l2p = pmap_l1_to_l2(l1p, addr);
4622 if (l2p == NULL) /* No l2 */
4625 l2 = pmap_load(l2p);
4626 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
4629 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4630 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
4631 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4632 val = MINCORE_SUPER | MINCORE_INCORE;
4633 if (pmap_page_dirty(l2))
4634 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4635 if ((l2 & ATTR_AF) == ATTR_AF)
4636 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4640 l3p = pmap_l2_to_l3(l2p, addr);
4641 if (l3p == NULL) /* No l3 */
4644 l3 = pmap_load(l2p);
4645 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
4648 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
4649 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
4650 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4651 val = MINCORE_INCORE;
4652 if (pmap_page_dirty(l3))
4653 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4654 if ((l3 & ATTR_AF) == ATTR_AF)
4655 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4659 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4660 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4661 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4662 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4665 PA_UNLOCK_COND(*locked_pa);
4672 pmap_activate(struct thread *td)
4677 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4678 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
4679 __asm __volatile("msr ttbr0_el1, %0" : :
4680 "r"(td->td_proc->p_md.md_l0addr));
4681 pmap_invalidate_all(pmap);
4686 pmap_switch(struct thread *old, struct thread *new)
4688 pcpu_bp_harden bp_harden;
4691 /* Store the new curthread */
4692 PCPU_SET(curthread, new);
4694 /* And the new pcb */
4696 PCPU_SET(curpcb, pcb);
4699 * TODO: We may need to flush the cache here if switching
4700 * to a user process.
4704 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
4706 /* Switch to the new pmap */
4707 "msr ttbr0_el1, %0 \n"
4710 /* Invalidate the TLB */
4715 : : "r"(new->td_proc->p_md.md_l0addr));
4718 * Stop userspace from training the branch predictor against
4719 * other processes. This will call into a CPU specific
4720 * function that clears the branch predictor state.
4722 bp_harden = PCPU_GET(bp_harden);
4723 if (bp_harden != NULL)
4731 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4734 if (va >= VM_MIN_KERNEL_ADDRESS) {
4735 cpu_icache_sync_range(va, sz);
4740 /* Find the length of data in this page to flush */
4741 offset = va & PAGE_MASK;
4742 len = imin(PAGE_SIZE - offset, sz);
4745 /* Extract the physical address & find it in the DMAP */
4746 pa = pmap_extract(pmap, va);
4748 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
4750 /* Move to the next page */
4753 /* Set the length for the next iteration */
4754 len = imin(PAGE_SIZE, sz);
4760 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
4766 switch (ESR_ELx_EXCEPTION(esr)) {
4767 case EXCP_INSN_ABORT_L:
4768 case EXCP_INSN_ABORT:
4769 case EXCP_DATA_ABORT_L:
4770 case EXCP_DATA_ABORT:
4773 return (KERN_FAILURE);
4776 /* Data and insn aborts use same encoding for FCS field. */
4778 switch (esr & ISS_DATA_DFSC_MASK) {
4779 case ISS_DATA_DFSC_TF_L0:
4780 case ISS_DATA_DFSC_TF_L1:
4781 case ISS_DATA_DFSC_TF_L2:
4782 case ISS_DATA_DFSC_TF_L3:
4783 /* Ask the MMU to check the address */
4784 intr = intr_disable();
4785 if (pmap == kernel_pmap)
4786 par = arm64_address_translate_s1e1r(far);
4788 par = arm64_address_translate_s1e0r(far);
4792 * If the translation was successful the address was invalid
4793 * due to a break-before-make sequence. We can unlock and
4794 * return success to the trap handler.
4796 if (PAR_SUCCESS(par)) {
4798 return (KERN_SUCCESS);
4807 return (KERN_FAILURE);
4811 * Increase the starting virtual address of the given mapping if a
4812 * different alignment might result in more superpage mappings.
4815 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4816 vm_offset_t *addr, vm_size_t size)
4818 vm_offset_t superpage_offset;
4822 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4823 offset += ptoa(object->pg_color);
4824 superpage_offset = offset & L2_OFFSET;
4825 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4826 (*addr & L2_OFFSET) == superpage_offset)
4828 if ((*addr & L2_OFFSET) < superpage_offset)
4829 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4831 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4835 * Get the kernel virtual address of a set of physical pages. If there are
4836 * physical addresses not covered by the DMAP perform a transient mapping
4837 * that will be removed when calling pmap_unmap_io_transient.
4839 * \param page The pages the caller wishes to obtain the virtual
4840 * address on the kernel memory map.
4841 * \param vaddr On return contains the kernel virtual memory address
4842 * of the pages passed in the page parameter.
4843 * \param count Number of pages passed in.
4844 * \param can_fault TRUE if the thread using the mapped pages can take
4845 * page faults, FALSE otherwise.
4847 * \returns TRUE if the caller must call pmap_unmap_io_transient when
4848 * finished or FALSE otherwise.
4852 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4853 boolean_t can_fault)
4856 boolean_t needs_mapping;
4860 * Allocate any KVA space that we need, this is done in a separate
4861 * loop to prevent calling vmem_alloc while pinned.
4863 needs_mapping = FALSE;
4864 for (i = 0; i < count; i++) {
4865 paddr = VM_PAGE_TO_PHYS(page[i]);
4866 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
4867 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4868 M_BESTFIT | M_WAITOK, &vaddr[i]);
4869 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4870 needs_mapping = TRUE;
4872 vaddr[i] = PHYS_TO_DMAP(paddr);
4876 /* Exit early if everything is covered by the DMAP */
4882 for (i = 0; i < count; i++) {
4883 paddr = VM_PAGE_TO_PHYS(page[i]);
4884 if (!PHYS_IN_DMAP(paddr)) {
4886 "pmap_map_io_transient: TODO: Map out of DMAP data");
4890 return (needs_mapping);
4894 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4895 boolean_t can_fault)
4902 for (i = 0; i < count; i++) {
4903 paddr = VM_PAGE_TO_PHYS(page[i]);
4904 if (!PHYS_IN_DMAP(paddr)) {
4905 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");