sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 #include "opt_bnx.h"
  37 #include "opt_ifpoll.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <netinet/ip.h>
  54 #include <netinet/tcp.h>
  55
  56 #include <net/bpf.h>
  57 #include <net/ethernet.h>
  58 #include <net/if.h>
  59 #include <net/if_arp.h>
  60 #include <net/if_dl.h>
  61 #include <net/if_media.h>
  62 #include <net/if_poll.h>
  63 #include <net/if_types.h>
  64 #include <net/ifq_var.h>
  65 #include <net/vlan/if_vlan_var.h>
  66 #include <net/vlan/if_vlan_ether.h>
  67
  68 #include <dev/netif/mii_layer/mii.h>
  69 #include <dev/netif/mii_layer/miivar.h>
  70 #include <dev/netif/mii_layer/brgphyreg.h>
  71
  72 #include <bus/pci/pcidevs.h>
  73 #include <bus/pci/pcireg.h>
  74 #include <bus/pci/pcivar.h>
  75
  76 #include <dev/netif/bge/if_bgereg.h>
  77 #include <dev/netif/bnx/if_bnxvar.h>
  78
  79 /* "device miibus" required.  See GENERIC if you get errors here. */
  80 #include "miibus_if.h"
  81
  82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  83
  84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
  85
  86 static const struct bnx_type {
  87         uint16_t                bnx_vid;
  88         uint16_t                bnx_did;
  89         char                    *bnx_name;
  90 } bnx_devs[] = {
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  92                 "Broadcom BCM5717 Gigabit Ethernet" },
  93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
  94                 "Broadcom BCM5717C Gigabit Ethernet" },
  95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  96                 "Broadcom BCM5718 Gigabit Ethernet" },
  97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  98                 "Broadcom BCM5719 Gigabit Ethernet" },
  99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
 100                 "Broadcom BCM5720 Gigabit Ethernet" },
 101
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
 103                 "Broadcom BCM5725 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
 105                 "Broadcom BCM5727 Gigabit Ethernet" },
 106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
 107                 "Broadcom BCM5762 Gigabit Ethernet" },
 108
 109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
 110                 "Broadcom BCM57761 Gigabit Ethernet" },
 111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
 112                 "Broadcom BCM57762 Gigabit Ethernet" },
 113         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 114                 "Broadcom BCM57765 Gigabit Ethernet" },
 115         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
 116                 "Broadcom BCM57766 Gigabit Ethernet" },
 117         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
 118                 "Broadcom BCM57781 Gigabit Ethernet" },
 119         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
 120                 "Broadcom BCM57782 Gigabit Ethernet" },
 121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 122                 "Broadcom BCM57785 Gigabit Ethernet" },
 123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
 124                 "Broadcom BCM57786 Gigabit Ethernet" },
 125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
 126                 "Broadcom BCM57791 Fast Ethernet" },
 127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 128                 "Broadcom BCM57795 Fast Ethernet" },
 129
 130         { 0, 0, NULL }
 131 };
 132
 133 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 134 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 135 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 136 #define BNX_IS_57765_FAMILY(sc)  \
 137         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 138
 139 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 140
 141 static int      bnx_probe(device_t);
 142 static int      bnx_attach(device_t);
 143 static int      bnx_detach(device_t);
 144 static void     bnx_shutdown(device_t);
 145 static int      bnx_suspend(device_t);
 146 static int      bnx_resume(device_t);
 147 static int      bnx_miibus_readreg(device_t, int, int);
 148 static int      bnx_miibus_writereg(device_t, int, int, int);
 149 static void     bnx_miibus_statchg(device_t);
 150
 151 #ifdef IFPOLL_ENABLE
 152 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
 153 static void     bnx_npoll_compat(struct ifnet *, void *, int);
 154 #endif
 155 static void     bnx_intr_legacy(void *);
 156 static void     bnx_msi(void *);
 157 static void     bnx_msi_oneshot(void *);
 158 static void     bnx_intr(struct bnx_softc *);
 159 static void     bnx_enable_intr(struct bnx_softc *);
 160 static void     bnx_disable_intr(struct bnx_softc *);
 161 static void     bnx_txeof(struct bnx_softc *, uint16_t);
 162 static void     bnx_rxeof(struct bnx_softc *, uint16_t, int);
 163
 164 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
 165 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 166 static void     bnx_init(void *);
 167 static void     bnx_stop(struct bnx_softc *);
 168 static void     bnx_watchdog(struct ifnet *);
 169 static int      bnx_ifmedia_upd(struct ifnet *);
 170 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 171 static void     bnx_tick(void *);
 172
 173 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 174 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 175 static struct bnx_jslot
 176                 *bnx_jalloc(struct bnx_softc *);
 177 static void     bnx_jfree(void *);
 178 static void     bnx_jref(void *);
 179 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
 180 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 181 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
 182 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 183 static int      bnx_init_rx_ring_std(struct bnx_softc *);
 184 static void     bnx_free_rx_ring_std(struct bnx_softc *);
 185 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 186 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 187 static void     bnx_free_tx_ring(struct bnx_softc *);
 188 static int      bnx_init_tx_ring(struct bnx_softc *);
 189 static int      bnx_dma_alloc(struct bnx_softc *);
 190 static void     bnx_dma_free(struct bnx_softc *);
 191 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 192                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 193 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 194 static struct mbuf *
 195                 bnx_defrag_shortdma(struct mbuf *);
 196 static int      bnx_encap(struct bnx_softc *, struct mbuf **,
 197                         uint32_t *, int *);
 198 static int      bnx_setup_tso(struct bnx_softc *, struct mbuf **,
 199                     uint16_t *, uint16_t *);
 200
 201 static void     bnx_reset(struct bnx_softc *);
 202 static int      bnx_chipinit(struct bnx_softc *);
 203 static int      bnx_blockinit(struct bnx_softc *);
 204 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 205 static void     bnx_enable_msi(struct bnx_softc *sc);
 206 static void     bnx_setmulti(struct bnx_softc *);
 207 static void     bnx_setpromisc(struct bnx_softc *);
 208 static void     bnx_stats_update_regs(struct bnx_softc *);
 209 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 210
 211 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 212 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 213 #ifdef notdef
 214 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 215 #endif
 216 static void     bnx_writereg_ind(struct bnx_softc *, uint32_t, uint32_t);
 217 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 218 static void     bnx_writembx(struct bnx_softc *, int, int);
 219 static uint8_t  bnx_nvram_getbyte(struct bnx_softc *, int, uint8_t *);
 220 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 221 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 222 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 223
 224 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 225 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 226 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 227 static void     bnx_link_poll(struct bnx_softc *);
 228
 229 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 230 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 231 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 232 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 233
 234 static void     bnx_coal_change(struct bnx_softc *);
 235 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 236 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 237 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 238 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 239 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 240 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 241 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 242                     int, int, uint32_t);
 243
 244 static int      bnx_msi_enable = 1;
 245 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 246
 247 static device_method_t bnx_methods[] = {
 248         /* Device interface */
 249         DEVMETHOD(device_probe,         bnx_probe),
 250         DEVMETHOD(device_attach,        bnx_attach),
 251         DEVMETHOD(device_detach,        bnx_detach),
 252         DEVMETHOD(device_shutdown,      bnx_shutdown),
 253         DEVMETHOD(device_suspend,       bnx_suspend),
 254         DEVMETHOD(device_resume,        bnx_resume),
 255
 256         /* bus interface */
 257         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 258         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 259
 260         /* MII interface */
 261         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 262         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 263         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 264
 265         DEVMETHOD_END
 266 };
 267
 268 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 269 static devclass_t bnx_devclass;
 270
 271 DECLARE_DUMMY_MODULE(if_bnx);
 272 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 273 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 274
 275 static uint32_t
 276 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 277 {
 278         device_t dev = sc->bnx_dev;
 279         uint32_t val;
 280
 281         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 282             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 283                 return 0;
 284
 285         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 286         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 287         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 288         return (val);
 289 }
 290
 291 static void
 292 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 293 {
 294         device_t dev = sc->bnx_dev;
 295
 296         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 297             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 298                 return;
 299
 300         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 301         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 302         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 303 }
 304
 305 #ifdef notdef
 306 static uint32_t
 307 bnx_readreg_ind(struct bnx_softc *sc, uin32_t off)
 308 {
 309         device_t dev = sc->bnx_dev;
 310
 311         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 312         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 313 }
 314 #endif
 315
 316 static void
 317 bnx_writereg_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 318 {
 319         device_t dev = sc->bnx_dev;
 320
 321         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 322         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 323 }
 324
 325 static void
 326 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 327 {
 328         CSR_WRITE_4(sc, off, val);
 329 }
 330
 331 static void
 332 bnx_writembx(struct bnx_softc *sc, int off, int val)
 333 {
 334         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
 335                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 336
 337         CSR_WRITE_4(sc, off, val);
 338 }
 339
 340 static uint8_t
 341 bnx_nvram_getbyte(struct bnx_softc *sc, int addr, uint8_t *dest)
 342 {
 343         uint32_t access, byte = 0;
 344         int i;
 345
 346         /* Lock. */
 347         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 348         for (i = 0; i < 8000; i++) {
 349                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 350                         break;
 351                 DELAY(20);
 352         }
 353         if (i == 8000)
 354                 return (1);
 355
 356         /* Enable access. */
 357         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 358         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 359
 360         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 361         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 362         for (i = 0; i < BNX_TIMEOUT * 10; i++) {
 363                 DELAY(10);
 364                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 365                         DELAY(10);
 366                         break;
 367                 }
 368         }
 369
 370         if (i == BNX_TIMEOUT * 10) {
 371                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 372                 return (1);
 373         }
 374
 375         /* Get result. */
 376         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 377
 378         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 379
 380         /* Disable access. */
 381         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 382
 383         /* Unlock. */
 384         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 385         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 386
 387         return (0);
 388 }
 389
 390 /*
 391  * Read a sequence of bytes from NVRAM.
 392  */
 393 static int
 394 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 395 {
 396         int err = 0, i;
 397         uint8_t byte = 0;
 398
 399         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 400                 return (1);
 401
 402         for (i = 0; i < cnt; i++) {
 403                 err = bnx_nvram_getbyte(sc, off + i, &byte);
 404                 if (err)
 405                         break;
 406                 *(dest + i) = byte;
 407         }
 408
 409         return (err ? 1 : 0);
 410 }
 411
 412 /*
 413  * Read a byte of data stored in the EEPROM at address 'addr.' The
 414  * BCM570x supports both the traditional bitbang interface and an
 415  * auto access interface for reading the EEPROM. We use the auto
 416  * access method.
 417  */
 418 static uint8_t
 419 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 420 {
 421         int i;
 422         uint32_t byte = 0;
 423
 424         /*
 425          * Enable use of auto EEPROM access so we can avoid
 426          * having to use the bitbang method.
 427          */
 428         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 429
 430         /* Reset the EEPROM, load the clock period. */
 431         CSR_WRITE_4(sc, BGE_EE_ADDR,
 432             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 433         DELAY(20);
 434
 435         /* Issue the read EEPROM command. */
 436         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 437
 438         /* Wait for completion */
 439         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 440                 DELAY(10);
 441                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 442                         break;
 443         }
 444
 445         if (i == BNX_TIMEOUT) {
 446                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 447                 return(1);
 448         }
 449
 450         /* Get result. */
 451         byte = CSR_READ_4(sc, BGE_EE_DATA);
 452
 453         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 454
 455         return(0);
 456 }
 457
 458 /*
 459  * Read a sequence of bytes from the EEPROM.
 460  */
 461 static int
 462 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 463 {
 464         size_t i;
 465         int err;
 466         uint8_t byte;
 467
 468         for (byte = 0, err = 0, i = 0; i < len; i++) {
 469                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 470                 if (err)
 471                         break;
 472                 *(dest + i) = byte;
 473         }
 474
 475         return(err ? 1 : 0);
 476 }
 477
 478 static int
 479 bnx_miibus_readreg(device_t dev, int phy, int reg)
 480 {
 481         struct bnx_softc *sc = device_get_softc(dev);
 482         uint32_t val;
 483         int i;
 484
 485         KASSERT(phy == sc->bnx_phyno,
 486             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 487
 488         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 489         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 490                 CSR_WRITE_4(sc, BGE_MI_MODE,
 491                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 492                 DELAY(80);
 493         }
 494
 495         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 496             BGE_MIPHY(phy) | BGE_MIREG(reg));
 497
 498         /* Poll for the PHY register access to complete. */
 499         for (i = 0; i < BNX_TIMEOUT; i++) {
 500                 DELAY(10);
 501                 val = CSR_READ_4(sc, BGE_MI_COMM);
 502                 if ((val & BGE_MICOMM_BUSY) == 0) {
 503                         DELAY(5);
 504                         val = CSR_READ_4(sc, BGE_MI_COMM);
 505                         break;
 506                 }
 507         }
 508         if (i == BNX_TIMEOUT) {
 509                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 510                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 511                 val = 0;
 512         }
 513
 514         /* Restore the autopoll bit if necessary. */
 515         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 516                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 517                 DELAY(80);
 518         }
 519
 520         if (val & BGE_MICOMM_READFAIL)
 521                 return 0;
 522
 523         return (val & 0xFFFF);
 524 }
 525
 526 static int
 527 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 528 {
 529         struct bnx_softc *sc = device_get_softc(dev);
 530         int i;
 531
 532         KASSERT(phy == sc->bnx_phyno,
 533             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 534
 535         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 536             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 537                return 0;
 538
 539         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 540         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 541                 CSR_WRITE_4(sc, BGE_MI_MODE,
 542                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 543                 DELAY(80);
 544         }
 545
 546         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 547             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 548
 549         for (i = 0; i < BNX_TIMEOUT; i++) {
 550                 DELAY(10);
 551                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 552                         DELAY(5);
 553                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 554                         break;
 555                 }
 556         }
 557         if (i == BNX_TIMEOUT) {
 558                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 559                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 560         }
 561
 562         /* Restore the autopoll bit if necessary. */
 563         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 564                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 565                 DELAY(80);
 566         }
 567
 568         return 0;
 569 }
 570
 571 static void
 572 bnx_miibus_statchg(device_t dev)
 573 {
 574         struct bnx_softc *sc;
 575         struct mii_data *mii;
 576
 577         sc = device_get_softc(dev);
 578         mii = device_get_softc(sc->bnx_miibus);
 579
 580         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 581             (IFM_ACTIVE | IFM_AVALID)) {
 582                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 583                 case IFM_10_T:
 584                 case IFM_100_TX:
 585                         sc->bnx_link = 1;
 586                         break;
 587                 case IFM_1000_T:
 588                 case IFM_1000_SX:
 589                 case IFM_2500_SX:
 590                         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 591                                 sc->bnx_link = 1;
 592                         else
 593                                 sc->bnx_link = 0;
 594                         break;
 595                 default:
 596                         sc->bnx_link = 0;
 597                         break;
 598                 }
 599         } else {
 600                 sc->bnx_link = 0;
 601         }
 602         if (sc->bnx_link == 0)
 603                 return;
 604
 605         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 606         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 607             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 608                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 609         } else {
 610                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 611         }
 612
 613         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 614                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 615         } else {
 616                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 617         }
 618 }
 619
 620 /*
 621  * Memory management for jumbo frames.
 622  */
 623 static int
 624 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 625 {
 626         struct ifnet *ifp = &sc->arpcom.ac_if;
 627         struct bnx_jslot *entry;
 628         uint8_t *ptr;
 629         bus_addr_t paddr;
 630         int i, error;
 631
 632         /*
 633          * Create tag for jumbo mbufs.
 634          * This is really a bit of a kludge. We allocate a special
 635          * jumbo buffer pool which (thanks to the way our DMA
 636          * memory allocation works) will consist of contiguous
 637          * pages. This means that even though a jumbo buffer might
 638          * be larger than a page size, we don't really need to
 639          * map it into more than one DMA segment. However, the
 640          * default mbuf tag will result in multi-segment mappings,
 641          * so we have to create a special jumbo mbuf tag that
 642          * lets us get away with mapping the jumbo buffers as
 643          * a single segment. I think eventually the driver should
 644          * be changed so that it uses ordinary mbufs and cluster
 645          * buffers, i.e. jumbo frames can span multiple DMA
 646          * descriptors. But that's a project for another day.
 647          */
 648
 649         /*
 650          * Create DMA stuffs for jumbo RX ring.
 651          */
 652         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 653                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 654                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 655                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 656                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 657         if (error) {
 658                 if_printf(ifp, "could not create jumbo RX ring\n");
 659                 return error;
 660         }
 661
 662         /*
 663          * Create DMA stuffs for jumbo buffer block.
 664          */
 665         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 666                                     &sc->bnx_cdata.bnx_jumbo_tag,
 667                                     &sc->bnx_cdata.bnx_jumbo_map,
 668                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 669                                     &paddr);
 670         if (error) {
 671                 if_printf(ifp, "could not create jumbo buffer\n");
 672                 return error;
 673         }
 674
 675         SLIST_INIT(&sc->bnx_jfree_listhead);
 676
 677         /*
 678          * Now divide it up into 9K pieces and save the addresses
 679          * in an array. Note that we play an evil trick here by using
 680          * the first few bytes in the buffer to hold the the address
 681          * of the softc structure for this interface. This is because
 682          * bnx_jfree() needs it, but it is called by the mbuf management
 683          * code which will not pass it to us explicitly.
 684          */
 685         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 686                 entry = &sc->bnx_cdata.bnx_jslots[i];
 687                 entry->bnx_sc = sc;
 688                 entry->bnx_buf = ptr;
 689                 entry->bnx_paddr = paddr;
 690                 entry->bnx_inuse = 0;
 691                 entry->bnx_slot = i;
 692                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 693
 694                 ptr += BNX_JLEN;
 695                 paddr += BNX_JLEN;
 696         }
 697         return 0;
 698 }
 699
 700 static void
 701 bnx_free_jumbo_mem(struct bnx_softc *sc)
 702 {
 703         /* Destroy jumbo RX ring. */
 704         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 705                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 706                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 707
 708         /* Destroy jumbo buffer block. */
 709         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 710                            sc->bnx_cdata.bnx_jumbo_map,
 711                            sc->bnx_ldata.bnx_jumbo_buf);
 712 }
 713
 714 /*
 715  * Allocate a jumbo buffer.
 716  */
 717 static struct bnx_jslot *
 718 bnx_jalloc(struct bnx_softc *sc)
 719 {
 720         struct bnx_jslot *entry;
 721
 722         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 723         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 724         if (entry) {
 725                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 726                 entry->bnx_inuse = 1;
 727         } else {
 728                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 729         }
 730         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 731         return(entry);
 732 }
 733
 734 /*
 735  * Adjust usage count on a jumbo buffer.
 736  */
 737 static void
 738 bnx_jref(void *arg)
 739 {
 740         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 741         struct bnx_softc *sc = entry->bnx_sc;
 742
 743         if (sc == NULL)
 744                 panic("bnx_jref: can't find softc pointer!");
 745
 746         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 747                 panic("bnx_jref: asked to reference buffer "
 748                     "that we don't manage!");
 749         } else if (entry->bnx_inuse == 0) {
 750                 panic("bnx_jref: buffer already free!");
 751         } else {
 752                 atomic_add_int(&entry->bnx_inuse, 1);
 753         }
 754 }
 755
 756 /*
 757  * Release a jumbo buffer.
 758  */
 759 static void
 760 bnx_jfree(void *arg)
 761 {
 762         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 763         struct bnx_softc *sc = entry->bnx_sc;
 764
 765         if (sc == NULL)
 766                 panic("bnx_jfree: can't find softc pointer!");
 767
 768         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 769                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 770         } else if (entry->bnx_inuse == 0) {
 771                 panic("bnx_jfree: buffer already free!");
 772         } else {
 773                 /*
 774                  * Possible MP race to 0, use the serializer.  The atomic insn
 775                  * is still needed for races against bnx_jref().
 776                  */
 777                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 778                 atomic_subtract_int(&entry->bnx_inuse, 1);
 779                 if (entry->bnx_inuse == 0) {
 780                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 781                                           entry, jslot_link);
 782                 }
 783                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 784         }
 785 }
 786
 787
 788 /*
 789  * Intialize a standard receive ring descriptor.
 790  */
 791 static int
 792 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
 793 {
 794         struct mbuf *m_new = NULL;
 795         bus_dma_segment_t seg;
 796         bus_dmamap_t map;
 797         int error, nsegs;
 798
 799         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 800         if (m_new == NULL)
 801                 return ENOBUFS;
 802         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 803         m_adj(m_new, ETHER_ALIGN);
 804
 805         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
 806                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
 807                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 808         if (error) {
 809                 m_freem(m_new);
 810                 return error;
 811         }
 812
 813         if (!init) {
 814                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
 815                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
 816                                 BUS_DMASYNC_POSTREAD);
 817                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 818                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 819         }
 820
 821         map = sc->bnx_cdata.bnx_rx_tmpmap;
 822         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
 823         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
 824
 825         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
 826         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
 827
 828         bnx_setup_rxdesc_std(sc, i);
 829         return 0;
 830 }
 831
 832 static void
 833 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
 834 {
 835         struct bnx_rxchain *rc;
 836         struct bge_rx_bd *r;
 837
 838         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 839         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
 840
 841         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 842         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 843         r->bge_len = rc->bnx_mbuf->m_len;
 844         r->bge_idx = i;
 845         r->bge_flags = BGE_RXBDFLAG_END;
 846 }
 847
 848 /*
 849  * Initialize a jumbo receive ring descriptor. This allocates
 850  * a jumbo buffer from the pool managed internally by the driver.
 851  */
 852 static int
 853 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 854 {
 855         struct mbuf *m_new = NULL;
 856         struct bnx_jslot *buf;
 857         bus_addr_t paddr;
 858
 859         /* Allocate the mbuf. */
 860         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 861         if (m_new == NULL)
 862                 return ENOBUFS;
 863
 864         /* Allocate the jumbo buffer */
 865         buf = bnx_jalloc(sc);
 866         if (buf == NULL) {
 867                 m_freem(m_new);
 868                 return ENOBUFS;
 869         }
 870
 871         /* Attach the buffer to the mbuf. */
 872         m_new->m_ext.ext_arg = buf;
 873         m_new->m_ext.ext_buf = buf->bnx_buf;
 874         m_new->m_ext.ext_free = bnx_jfree;
 875         m_new->m_ext.ext_ref = bnx_jref;
 876         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 877
 878         m_new->m_flags |= M_EXT;
 879
 880         m_new->m_data = m_new->m_ext.ext_buf;
 881         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 882
 883         paddr = buf->bnx_paddr;
 884         m_adj(m_new, ETHER_ALIGN);
 885         paddr += ETHER_ALIGN;
 886
 887         /* Save necessary information */
 888         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
 889         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
 890
 891         /* Set up the descriptor. */
 892         bnx_setup_rxdesc_jumbo(sc, i);
 893         return 0;
 894 }
 895
 896 static void
 897 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 898 {
 899         struct bge_rx_bd *r;
 900         struct bnx_rxchain *rc;
 901
 902         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 903         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 904
 905         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 906         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 907         r->bge_len = rc->bnx_mbuf->m_len;
 908         r->bge_idx = i;
 909         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 910 }
 911
 912 static int
 913 bnx_init_rx_ring_std(struct bnx_softc *sc)
 914 {
 915         int i, error;
 916
 917         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 918                 error = bnx_newbuf_std(sc, i, 1);
 919                 if (error)
 920                         return error;
 921         }
 922
 923         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
 924         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
 925
 926         return(0);
 927 }
 928
 929 static void
 930 bnx_free_rx_ring_std(struct bnx_softc *sc)
 931 {
 932         int i;
 933
 934         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 935                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 936
 937                 if (rc->bnx_mbuf != NULL) {
 938                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 939                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 940                         m_freem(rc->bnx_mbuf);
 941                         rc->bnx_mbuf = NULL;
 942                 }
 943                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
 944                     sizeof(struct bge_rx_bd));
 945         }
 946 }
 947
 948 static int
 949 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 950 {
 951         struct bge_rcb *rcb;
 952         int i, error;
 953
 954         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 955                 error = bnx_newbuf_jumbo(sc, i, 1);
 956                 if (error)
 957                         return error;
 958         }
 959
 960         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 961
 962         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 963         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 964         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 965
 966         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 967
 968         return(0);
 969 }
 970
 971 static void
 972 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 973 {
 974         int i;
 975
 976         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 977                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 978
 979                 if (rc->bnx_mbuf != NULL) {
 980                         m_freem(rc->bnx_mbuf);
 981                         rc->bnx_mbuf = NULL;
 982                 }
 983                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 984                     sizeof(struct bge_rx_bd));
 985         }
 986 }
 987
 988 static void
 989 bnx_free_tx_ring(struct bnx_softc *sc)
 990 {
 991         int i;
 992
 993         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 994                 if (sc->bnx_cdata.bnx_tx_chain[i] != NULL) {
 995                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
 996                                           sc->bnx_cdata.bnx_tx_dmamap[i]);
 997                         m_freem(sc->bnx_cdata.bnx_tx_chain[i]);
 998                         sc->bnx_cdata.bnx_tx_chain[i] = NULL;
 999                 }
1000                 bzero(&sc->bnx_ldata.bnx_tx_ring[i],
1001                     sizeof(struct bge_tx_bd));
1002         }
1003 }
1004
1005 static int
1006 bnx_init_tx_ring(struct bnx_softc *sc)
1007 {
1008         sc->bnx_txcnt = 0;
1009         sc->bnx_tx_saved_considx = 0;
1010         sc->bnx_tx_prodidx = 0;
1011
1012         /* Initialize transmit producer index for host-memory send ring. */
1013         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bnx_tx_prodidx);
1014         bnx_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1015
1016         return(0);
1017 }
1018
1019 static void
1020 bnx_setmulti(struct bnx_softc *sc)
1021 {
1022         struct ifnet *ifp;
1023         struct ifmultiaddr *ifma;
1024         uint32_t hashes[4] = { 0, 0, 0, 0 };
1025         int h, i;
1026
1027         ifp = &sc->arpcom.ac_if;
1028
1029         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1030                 for (i = 0; i < 4; i++)
1031                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1032                 return;
1033         }
1034
1035         /* First, zot all the existing filters. */
1036         for (i = 0; i < 4; i++)
1037                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1038
1039         /* Now program new ones. */
1040         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1041                 if (ifma->ifma_addr->sa_family != AF_LINK)
1042                         continue;
1043                 h = ether_crc32_le(
1044                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1045                     ETHER_ADDR_LEN) & 0x7f;
1046                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1047         }
1048
1049         for (i = 0; i < 4; i++)
1050                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1051 }
1052
1053 /*
1054  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1055  * self-test results.
1056  */
1057 static int
1058 bnx_chipinit(struct bnx_softc *sc)
1059 {
1060         uint32_t dma_rw_ctl, mode_ctl;
1061         int i;
1062
1063         /* Set endian type before we access any non-PCI registers. */
1064         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1065             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1066
1067         /* Clear the MAC control register */
1068         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1069
1070         /*
1071          * Clear the MAC statistics block in the NIC's
1072          * internal memory.
1073          */
1074         for (i = BGE_STATS_BLOCK;
1075             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1076                 BNX_MEMWIN_WRITE(sc, i, 0);
1077
1078         for (i = BGE_STATUS_BLOCK;
1079             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1080                 BNX_MEMWIN_WRITE(sc, i, 0);
1081
1082         if (BNX_IS_57765_FAMILY(sc)) {
1083                 uint32_t val;
1084
1085                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1086                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1087                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1088
1089                         /* Access the lower 1K of PL PCI-E block registers. */
1090                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1091                             val | BGE_MODECTL_PCIE_PL_SEL);
1092
1093                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1094                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1095                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1096
1097                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1098                 }
1099                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1100                         /* Fix transmit hangs */
1101                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1102                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1103                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1104
1105                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1106                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1107
1108                         /* Access the lower 1K of DL PCI-E block registers. */
1109                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1110                             val | BGE_MODECTL_PCIE_DL_SEL);
1111
1112                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1113                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1114                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1115                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1116
1117                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1118                 }
1119
1120                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1121                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1122                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1123                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1124         }
1125
1126         /*
1127          * Set up the PCI DMA control register.
1128          */
1129         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1130         /*
1131          * Disable 32bytes cache alignment for DMA write to host memory
1132          *
1133          * NOTE:
1134          * 64bytes cache alignment for DMA write to host memory is still
1135          * enabled.
1136          */
1137         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1138         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1139                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1140         /*
1141          * Enable HW workaround for controllers that misinterpret
1142          * a status tag update and leave interrupts permanently
1143          * disabled.
1144          */
1145         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1146             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1147             !BNX_IS_57765_FAMILY(sc))
1148                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1149         if (bootverbose) {
1150                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1151                     dma_rw_ctl);
1152         }
1153         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1154
1155         /*
1156          * Set up general mode register.
1157          */
1158         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1159             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1160         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1161
1162         /*
1163          * Disable memory write invalidate.  Apparently it is not supported
1164          * properly by these devices.  Also ensure that INTx isn't disabled,
1165          * as these chips need it even when using MSI.
1166          */
1167         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1168             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1169
1170         /* Set the timer prescaler (always 66Mhz) */
1171         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1172
1173         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1174                 DELAY(40);      /* XXX */
1175
1176                 /* Put PHY into ready state */
1177                 BNX_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1178                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1179                 DELAY(40);
1180         }
1181
1182         return(0);
1183 }
1184
1185 static int
1186 bnx_blockinit(struct bnx_softc *sc)
1187 {
1188         struct bge_rcb *rcb;
1189         bus_size_t vrcb;
1190         bge_hostaddr taddr;
1191         uint32_t val;
1192         int i, limit;
1193
1194         /*
1195          * Initialize the memory window pointer register so that
1196          * we can access the first 32K of internal NIC RAM. This will
1197          * allow us to set up the TX send ring RCBs and the RX return
1198          * ring RCBs, plus other things which live in NIC memory.
1199          */
1200         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1201
1202         /* Configure mbuf pool watermarks */
1203         if (BNX_IS_57765_PLUS(sc)) {
1204                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1205                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1206                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1207                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1208                 } else {
1209                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1210                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1211                 }
1212         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1213                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1214                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1215                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1216         } else {
1217                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1218                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1219                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1220         }
1221
1222         /* Configure DMA resource watermarks */
1223         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1224         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1225
1226         /* Enable buffer manager */
1227         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1228         /*
1229          * Change the arbitration algorithm of TXMBUF read request to
1230          * round-robin instead of priority based for BCM5719.  When
1231          * TXFIFO is almost empty, RDMA will hold its request until
1232          * TXFIFO is not almost empty.
1233          */
1234         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1235                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1236         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1237             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1238             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1239                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1240         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1241
1242         /* Poll for buffer manager start indication */
1243         for (i = 0; i < BNX_TIMEOUT; i++) {
1244                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1245                         break;
1246                 DELAY(10);
1247         }
1248
1249         if (i == BNX_TIMEOUT) {
1250                 if_printf(&sc->arpcom.ac_if,
1251                           "buffer manager failed to start\n");
1252                 return(ENXIO);
1253         }
1254
1255         /* Enable flow-through queues */
1256         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1257         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1258
1259         /* Wait until queue initialization is complete */
1260         for (i = 0; i < BNX_TIMEOUT; i++) {
1261                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1262                         break;
1263                 DELAY(10);
1264         }
1265
1266         if (i == BNX_TIMEOUT) {
1267                 if_printf(&sc->arpcom.ac_if,
1268                           "flow-through queue init failed\n");
1269                 return(ENXIO);
1270         }
1271
1272         /*
1273          * Summary of rings supported by the controller:
1274          *
1275          * Standard Receive Producer Ring
1276          * - This ring is used to feed receive buffers for "standard"
1277          *   sized frames (typically 1536 bytes) to the controller.
1278          *
1279          * Jumbo Receive Producer Ring
1280          * - This ring is used to feed receive buffers for jumbo sized
1281          *   frames (i.e. anything bigger than the "standard" frames)
1282          *   to the controller.
1283          *
1284          * Mini Receive Producer Ring
1285          * - This ring is used to feed receive buffers for "mini"
1286          *   sized frames to the controller.
1287          * - This feature required external memory for the controller
1288          *   but was never used in a production system.  Should always
1289          *   be disabled.
1290          *
1291          * Receive Return Ring
1292          * - After the controller has placed an incoming frame into a
1293          *   receive buffer that buffer is moved into a receive return
1294          *   ring.  The driver is then responsible to passing the
1295          *   buffer up to the stack.  Many versions of the controller
1296          *   support multiple RR rings.
1297          *
1298          * Send Ring
1299          * - This ring is used for outgoing frames.  Many versions of
1300          *   the controller support multiple send rings.
1301          */
1302
1303         /* Initialize the standard receive producer ring control block. */
1304         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1305         rcb->bge_hostaddr.bge_addr_lo =
1306             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1307         rcb->bge_hostaddr.bge_addr_hi =
1308             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1309         if (BNX_IS_57765_PLUS(sc)) {
1310                 /*
1311                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1312                  * Bits 15-2 : Maximum RX frame size
1313                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1314                  * Bit 0     : Reserved
1315                  */
1316                 rcb->bge_maxlen_flags =
1317                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1318         } else {
1319                 /*
1320                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1321                  * Bits 15-2 : Reserved (should be 0)
1322                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1323                  * Bit 0     : Reserved
1324                  */
1325                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1326         }
1327         if (BNX_IS_5717_PLUS(sc))
1328                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1329         else
1330                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1331         /* Write the standard receive producer ring control block. */
1332         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1333         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1334         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1335         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1336         /* Reset the standard receive producer ring producer index. */
1337         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1338
1339         /*
1340          * Initialize the jumbo RX producer ring control
1341          * block.  We set the 'ring disabled' bit in the
1342          * flags field until we're actually ready to start
1343          * using this ring (i.e. once we set the MTU
1344          * high enough to require it).
1345          */
1346         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1347                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1348                 /* Get the jumbo receive producer ring RCB parameters. */
1349                 rcb->bge_hostaddr.bge_addr_lo =
1350                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1351                 rcb->bge_hostaddr.bge_addr_hi =
1352                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1353                 rcb->bge_maxlen_flags =
1354                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1355                     BGE_RCB_FLAG_RING_DISABLED);
1356                 if (BNX_IS_5717_PLUS(sc))
1357                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1358                 else
1359                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1360                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1361                     rcb->bge_hostaddr.bge_addr_hi);
1362                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1363                     rcb->bge_hostaddr.bge_addr_lo);
1364                 /* Program the jumbo receive producer ring RCB parameters. */
1365                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1366                     rcb->bge_maxlen_flags);
1367                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1368                 /* Reset the jumbo receive producer ring producer index. */
1369                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1370         }
1371
1372         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1373         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
1374             (sc->bnx_chipid == BGE_CHIPID_BCM5906_A0 ||
1375              sc->bnx_chipid == BGE_CHIPID_BCM5906_A1 ||
1376              sc->bnx_chipid == BGE_CHIPID_BCM5906_A2)) {
1377                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1378                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1379         }
1380
1381         /*
1382          * The BD ring replenish thresholds control how often the
1383          * hardware fetches new BD's from the producer rings in host
1384          * memory.  Setting the value too low on a busy system can
1385          * starve the hardware and recue the throughpout.
1386          *
1387          * Set the BD ring replentish thresholds. The recommended
1388          * values are 1/8th the number of descriptors allocated to
1389          * each ring.
1390          */
1391         val = 8;
1392         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1393         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1394                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1395                     BGE_JUMBO_RX_RING_CNT/8);
1396         }
1397         if (BNX_IS_57765_PLUS(sc)) {
1398                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1399                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1400         }
1401
1402         /*
1403          * Disable all send rings by setting the 'ring disabled' bit
1404          * in the flags field of all the TX send ring control blocks,
1405          * located in NIC memory.
1406          */
1407         if (BNX_IS_5717_PLUS(sc))
1408                 limit = 4;
1409         else if (BNX_IS_57765_FAMILY(sc) ||
1410             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1411                 limit = 2;
1412         else
1413                 limit = 1;
1414         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1415         for (i = 0; i < limit; i++) {
1416                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1417                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1418                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1419                 vrcb += sizeof(struct bge_rcb);
1420         }
1421
1422         /* Configure send ring RCB 0 (we use only the first ring) */
1423         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1424         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_tx_ring_paddr);
1425         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1426         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1427         if (BNX_IS_5717_PLUS(sc)) {
1428                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1429         } else {
1430                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1431                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1432         }
1433         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1434             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1435
1436         /*
1437          * Disable all receive return rings by setting the
1438          * 'ring disabled' bit in the flags field of all the receive
1439          * return ring control blocks, located in NIC memory.
1440          */
1441         if (BNX_IS_5717_PLUS(sc)) {
1442                 /* Should be 17, use 16 until we get an SRAM map. */
1443                 limit = 16;
1444         } else if (BNX_IS_57765_FAMILY(sc) ||
1445             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1446                 limit = 4;
1447         } else {
1448                 limit = 1;
1449         }
1450         /* Disable all receive return rings. */
1451         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1452         for (i = 0; i < limit; i++) {
1453                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1454                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1455                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1456                     BGE_RCB_FLAG_RING_DISABLED);
1457                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1458                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1459                     (i * (sizeof(uint64_t))), 0);
1460                 vrcb += sizeof(struct bge_rcb);
1461         }
1462
1463         /*
1464          * Set up receive return ring 0.  Note that the NIC address
1465          * for RX return rings is 0x0.  The return rings live entirely
1466          * within the host, so the nicaddr field in the RCB isn't used.
1467          */
1468         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1469         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1470         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1471         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1472         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1473         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1474             BGE_RCB_MAXLEN_FLAGS(sc->bnx_return_ring_cnt, 0));
1475
1476         /* Set random backoff seed for TX */
1477         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1478             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1479             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1480             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1481             BGE_TX_BACKOFF_SEED_MASK);
1482
1483         /* Set inter-packet gap */
1484         val = 0x2620;
1485         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1486             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1487                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1488                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1489         }
1490         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1491
1492         /*
1493          * Specify which ring to use for packets that don't match
1494          * any RX rules.
1495          */
1496         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1497
1498         /*
1499          * Configure number of RX lists. One interrupt distribution
1500          * list, sixteen active lists, one bad frames class.
1501          */
1502         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1503
1504         /* Inialize RX list placement stats mask. */
1505         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1506         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1507
1508         /* Disable host coalescing until we get it set up */
1509         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1510
1511         /* Poll to make sure it's shut down. */
1512         for (i = 0; i < BNX_TIMEOUT; i++) {
1513                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1514                         break;
1515                 DELAY(10);
1516         }
1517
1518         if (i == BNX_TIMEOUT) {
1519                 if_printf(&sc->arpcom.ac_if,
1520                           "host coalescing engine failed to idle\n");
1521                 return(ENXIO);
1522         }
1523
1524         /* Set up host coalescing defaults */
1525         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1526         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1527         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1528         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1529         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1530         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1531
1532         /* Set up address of status block */
1533         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1534         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1535             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1536         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1537             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1538
1539         /* Set up status block partail update size. */
1540         val = BGE_STATBLKSZ_32BYTE;
1541 #if 0
1542         /*
1543          * Does not seem to have visible effect in both
1544          * bulk data (1472B UDP datagram) and tiny data
1545          * (18B UDP datagram) TX tests.
1546          */
1547         val |= BGE_HCCMODE_CLRTICK_TX;
1548 #endif
1549         /* Turn on host coalescing state machine */
1550         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1551
1552         /* Turn on RX BD completion state machine and enable attentions */
1553         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1554             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1555
1556         /* Turn on RX list placement state machine */
1557         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1558
1559         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1560             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1561             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1562             BGE_MACMODE_FRMHDR_DMA_ENB;
1563
1564         if (sc->bnx_flags & BNX_FLAG_TBI)
1565                 val |= BGE_PORTMODE_TBI;
1566         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1567                 val |= BGE_PORTMODE_GMII;
1568         else
1569                 val |= BGE_PORTMODE_MII;
1570
1571         /* Turn on DMA, clear stats */
1572         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1573
1574         /* Set misc. local control, enable interrupts on attentions */
1575         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1576
1577 #ifdef notdef
1578         /* Assert GPIO pins for PHY reset */
1579         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1580             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1581         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1582             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1583 #endif
1584
1585         /* Turn on write DMA state machine */
1586         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1587         /* Enable host coalescing bug fix. */
1588         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1589         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1590                 /* Request larger DMA burst size to get better performance. */
1591                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1592         }
1593         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1594         DELAY(40);
1595
1596         if (BNX_IS_57765_PLUS(sc)) {
1597                 uint32_t dmactl, dmactl_reg;
1598
1599                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1600                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1601                 else
1602                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1603
1604                 dmactl = CSR_READ_4(sc, dmactl_reg);
1605                 /*
1606                  * Adjust tx margin to prevent TX data corruption and
1607                  * fix internal FIFO overflow.
1608                  */
1609                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1610                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1611                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1612                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1613                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1614                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1615                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1616                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1617                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1618                 }
1619                 /*
1620                  * Enable fix for read DMA FIFO overruns.
1621                  * The fix is to limit the number of RX BDs
1622                  * the hardware would fetch at a fime.
1623                  */
1624                 CSR_WRITE_4(sc, dmactl_reg,
1625                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1626         }
1627
1628         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1629                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1630                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1631                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1632                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1633         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1634             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1635                 uint32_t ctrl_reg;
1636
1637                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1638                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1639                 else
1640                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1641
1642                 /*
1643                  * Allow 4KB burst length reads for non-LSO frames.
1644                  * Enable 512B burst length reads for buffer descriptors.
1645                  */
1646                 CSR_WRITE_4(sc, ctrl_reg,
1647                     CSR_READ_4(sc, ctrl_reg) |
1648                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1649                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1650         }
1651
1652         /* Turn on read DMA state machine */
1653         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1654         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1655                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1656         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1657             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1658             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1659                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1660                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1661                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1662         }
1663         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1664             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1665                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1666                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1667                 /*
1668                  * Allow multiple outstanding read requests from
1669                  * non-LSO read DMA engine.
1670                  */
1671                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1672         }
1673         if (sc->bnx_flags & BNX_FLAG_TSO)
1674                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1675         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1676         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1677         DELAY(40);
1678
1679         /* Turn on RX data completion state machine */
1680         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1681
1682         /* Turn on RX BD initiator state machine */
1683         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1684
1685         /* Turn on RX data and RX BD initiator state machine */
1686         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1687
1688         /* Turn on send BD completion state machine */
1689         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1690
1691         /* Turn on send data completion state machine */
1692         val = BGE_SDCMODE_ENABLE;
1693         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1694                 val |= BGE_SDCMODE_CDELAY;
1695         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1696
1697         /* Turn on send data initiator state machine */
1698         if (sc->bnx_flags & BNX_FLAG_TSO) {
1699                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1700                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1701         } else {
1702                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1703         }
1704
1705         /* Turn on send BD initiator state machine */
1706         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1707
1708         /* Turn on send BD selector state machine */
1709         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1710
1711         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1712         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1713             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1714
1715         /* ack/clear link change events */
1716         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1717             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1718             BGE_MACSTAT_LINK_CHANGED);
1719         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1720
1721         /*
1722          * Enable attention when the link has changed state for
1723          * devices that use auto polling.
1724          */
1725         if (sc->bnx_flags & BNX_FLAG_TBI) {
1726                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1727         } else {
1728                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1729                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1730                         DELAY(80);
1731                 }
1732         }
1733
1734         /*
1735          * Clear any pending link state attention.
1736          * Otherwise some link state change events may be lost until attention
1737          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1738          * It's not necessary on newer BCM chips - perhaps enabling link
1739          * state change attentions implies clearing pending attention.
1740          */
1741         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1742             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1743             BGE_MACSTAT_LINK_CHANGED);
1744
1745         /* Enable link state change attentions. */
1746         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1747
1748         return(0);
1749 }
1750
1751 /*
1752  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1753  * against our list and return its name if we find a match. Note
1754  * that since the Broadcom controller contains VPD support, we
1755  * can get the device name string from the controller itself instead
1756  * of the compiled-in string. This is a little slow, but it guarantees
1757  * we'll always announce the right product name.
1758  */
1759 static int
1760 bnx_probe(device_t dev)
1761 {
1762         const struct bnx_type *t;
1763         uint16_t product, vendor;
1764
1765         if (!pci_is_pcie(dev))
1766                 return ENXIO;
1767
1768         product = pci_get_device(dev);
1769         vendor = pci_get_vendor(dev);
1770
1771         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1772                 if (vendor == t->bnx_vid && product == t->bnx_did)
1773                         break;
1774         }
1775         if (t->bnx_name == NULL)
1776                 return ENXIO;
1777
1778         device_set_desc(dev, t->bnx_name);
1779         return 0;
1780 }
1781
1782 static int
1783 bnx_attach(device_t dev)
1784 {
1785         struct ifnet *ifp;
1786         struct bnx_softc *sc;
1787         uint32_t hwcfg = 0;
1788         int error = 0, rid, capmask;
1789         uint8_t ether_addr[ETHER_ADDR_LEN];
1790         uint16_t product;
1791         driver_intr_t *intr_func;
1792         uintptr_t mii_priv = 0;
1793         u_int intr_flags;
1794 #ifdef BNX_TSO_DEBUG
1795         char desc[32];
1796         int i;
1797 #endif
1798
1799         sc = device_get_softc(dev);
1800         sc->bnx_dev = dev;
1801         callout_init_mp(&sc->bnx_stat_timer);
1802         callout_init_mp(&sc->bnx_intr_timer);
1803         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1804
1805         product = pci_get_device(dev);
1806
1807 #ifndef BURN_BRIDGES
1808         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1809                 uint32_t irq, mem;
1810
1811                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1812                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1813
1814                 device_printf(dev, "chip is in D%d power mode "
1815                     "-- setting to D0\n", pci_get_powerstate(dev));
1816
1817                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1818
1819                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1820                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1821         }
1822 #endif  /* !BURN_BRIDGE */
1823
1824         /*
1825          * Map control/status registers.
1826          */
1827         pci_enable_busmaster(dev);
1828
1829         rid = BGE_PCI_BAR0;
1830         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1831             RF_ACTIVE);
1832
1833         if (sc->bnx_res == NULL) {
1834                 device_printf(dev, "couldn't map memory\n");
1835                 return ENXIO;
1836         }
1837
1838         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1839         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1840
1841         /* Save various chip information */
1842         sc->bnx_chipid =
1843             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1844             BGE_PCIMISCCTL_ASICREV_SHIFT;
1845         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1846                 /* All chips having dedicated ASICREV register have CPMU */
1847                 sc->bnx_flags |= BNX_FLAG_CPMU;
1848
1849                 switch (product) {
1850                 case PCI_PRODUCT_BROADCOM_BCM5717:
1851                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1852                 case PCI_PRODUCT_BROADCOM_BCM5718:
1853                 case PCI_PRODUCT_BROADCOM_BCM5719:
1854                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1855                 case PCI_PRODUCT_BROADCOM_BCM5725:
1856                 case PCI_PRODUCT_BROADCOM_BCM5727:
1857                 case PCI_PRODUCT_BROADCOM_BCM5762:
1858                         sc->bnx_chipid = pci_read_config(dev,
1859                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1860                         break;
1861
1862                 case PCI_PRODUCT_BROADCOM_BCM57761:
1863                 case PCI_PRODUCT_BROADCOM_BCM57762:
1864                 case PCI_PRODUCT_BROADCOM_BCM57765:
1865                 case PCI_PRODUCT_BROADCOM_BCM57766:
1866                 case PCI_PRODUCT_BROADCOM_BCM57781:
1867                 case PCI_PRODUCT_BROADCOM_BCM57782:
1868                 case PCI_PRODUCT_BROADCOM_BCM57785:
1869                 case PCI_PRODUCT_BROADCOM_BCM57786:
1870                 case PCI_PRODUCT_BROADCOM_BCM57791:
1871                 case PCI_PRODUCT_BROADCOM_BCM57795:
1872                         sc->bnx_chipid = pci_read_config(dev,
1873                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1874                         break;
1875
1876                 default:
1877                         sc->bnx_chipid = pci_read_config(dev,
1878                             BGE_PCI_PRODID_ASICREV, 4);
1879                         break;
1880                 }
1881         }
1882         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1883                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1884
1885         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1886         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1887
1888         switch (sc->bnx_asicrev) {
1889         case BGE_ASICREV_BCM5717:
1890         case BGE_ASICREV_BCM5719:
1891         case BGE_ASICREV_BCM5720:
1892                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1893                 break;
1894
1895         case BGE_ASICREV_BCM5762:
1896                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1897                 break;
1898
1899         case BGE_ASICREV_BCM57765:
1900         case BGE_ASICREV_BCM57766:
1901                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1902                 break;
1903         }
1904         sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1905
1906         sc->bnx_flags |= BNX_FLAG_TSO;
1907         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1908             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1909                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1910
1911         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1912             BNX_IS_57765_FAMILY(sc)) {
1913                 /*
1914                  * All BCM57785 and BCM5718 families chips have a bug that
1915                  * under certain situation interrupt will not be enabled
1916                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1917                  *
1918                  * While BCM5719 and BCM5720 have a hardware workaround
1919                  * which could fix the above bug.
1920                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1921                  * bnx_chipinit().
1922                  *
1923                  * For the rest of the chips in these two families, we will
1924                  * have to poll the status block at high rate (10ms currently)
1925                  * to check whether the interrupt is hosed or not.
1926                  * See bnx_intr_check() for details.
1927                  */
1928                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1929         }
1930
1931         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1932         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1933             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1934                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1935         else
1936                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1937         device_printf(dev, "CHIP ID 0x%08x; "
1938                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1939                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1940
1941         /*
1942          * Set various PHY quirk flags.
1943          */
1944
1945         capmask = MII_CAPMASK_DEFAULT;
1946         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1947             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1948                 /* 10/100 only */
1949                 capmask &= ~BMSR_EXTSTAT;
1950         }
1951
1952         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1953         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1954                 mii_priv |= BRGPHY_FLAG_5762_A0;
1955
1956         /*
1957          * Allocate interrupt
1958          */
1959         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1960             &intr_flags);
1961
1962         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1963             intr_flags);
1964         if (sc->bnx_irq == NULL) {
1965                 device_printf(dev, "couldn't map interrupt\n");
1966                 error = ENXIO;
1967                 goto fail;
1968         }
1969
1970         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1971                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1972                 bnx_enable_msi(sc);
1973         }
1974
1975         /* Initialize if_name earlier, so if_printf could be used */
1976         ifp = &sc->arpcom.ac_if;
1977         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1978
1979         /* Try to reset the chip. */
1980         bnx_reset(sc);
1981
1982         if (bnx_chipinit(sc)) {
1983                 device_printf(dev, "chip initialization failed\n");
1984                 error = ENXIO;
1985                 goto fail;
1986         }
1987
1988         /*
1989          * Get station address
1990          */
1991         error = bnx_get_eaddr(sc, ether_addr);
1992         if (error) {
1993                 device_printf(dev, "failed to read station address\n");
1994                 goto fail;
1995         }
1996
1997         if (BNX_IS_57765_PLUS(sc)) {
1998                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT;
1999         } else {
2000                 /* 5705/5750 limits RX return ring to 512 entries. */
2001                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2002         }
2003
2004         error = bnx_dma_alloc(sc);
2005         if (error)
2006                 goto fail;
2007
2008         /* Set default tuneable values. */
2009         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
2010         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
2011         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
2012         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
2013         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
2014         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
2015         sc->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
2016
2017         /* Set up ifnet structure */
2018         ifp->if_softc = sc;
2019         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2020         ifp->if_ioctl = bnx_ioctl;
2021         ifp->if_start = bnx_start;
2022 #ifdef IFPOLL_ENABLE
2023         ifp->if_npoll = bnx_npoll;
2024 #endif
2025         ifp->if_watchdog = bnx_watchdog;
2026         ifp->if_init = bnx_init;
2027         ifp->if_mtu = ETHERMTU;
2028         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2029         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2030         ifq_set_ready(&ifp->if_snd);
2031
2032         ifp->if_capabilities |= IFCAP_HWCSUM;
2033         ifp->if_hwassist = BNX_CSUM_FEATURES;
2034         if (sc->bnx_flags & BNX_FLAG_TSO) {
2035                 ifp->if_capabilities |= IFCAP_TSO;
2036                 ifp->if_hwassist |= CSUM_TSO;
2037         }
2038         ifp->if_capenable = ifp->if_capabilities;
2039
2040         /*
2041          * Figure out what sort of media we have by checking the
2042          * hardware config word in the first 32k of NIC internal memory,
2043          * or fall back to examining the EEPROM if necessary.
2044          * Note: on some BCM5700 cards, this value appears to be unset.
2045          * If that's the case, we have to rely on identifying the NIC
2046          * by its PCI subsystem ID, as we do below for the SysKonnect
2047          * SK-9D41.
2048          */
2049         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2050                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2051         } else {
2052                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2053                                     sizeof(hwcfg))) {
2054                         device_printf(dev, "failed to read EEPROM\n");
2055                         error = ENXIO;
2056                         goto fail;
2057                 }
2058                 hwcfg = ntohl(hwcfg);
2059         }
2060
2061         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2062         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2063             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2064                 sc->bnx_flags |= BNX_FLAG_TBI;
2065
2066         /* Setup MI MODE */
2067         if (sc->bnx_flags & BNX_FLAG_CPMU)
2068                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2069         else
2070                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2071
2072         /* Setup link status update stuffs */
2073         if (sc->bnx_flags & BNX_FLAG_TBI) {
2074                 sc->bnx_link_upd = bnx_tbi_link_upd;
2075                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2076         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2077                 sc->bnx_link_upd = bnx_autopoll_link_upd;
2078                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2079         } else {
2080                 sc->bnx_link_upd = bnx_copper_link_upd;
2081                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2082         }
2083
2084         /* Set default PHY address */
2085         sc->bnx_phyno = 1;
2086
2087         /*
2088          * PHY address mapping for various devices.
2089          *
2090          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2091          * ---------+-------+-------+-------+-------+
2092          * BCM57XX  |   1   |   X   |   X   |   X   |
2093          * BCM5704  |   1   |   X   |   1   |   X   |
2094          * BCM5717  |   1   |   8   |   2   |   9   |
2095          * BCM5719  |   1   |   8   |   2   |   9   |
2096          * BCM5720  |   1   |   8   |   2   |   9   |
2097          *
2098          * Other addresses may respond but they are not
2099          * IEEE compliant PHYs and should be ignored.
2100          */
2101         if (BNX_IS_5717_PLUS(sc)) {
2102                 int f;
2103
2104                 f = pci_get_function(dev);
2105                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2106                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2107                             BGE_SGDIGSTS_IS_SERDES)
2108                                 sc->bnx_phyno = f + 8;
2109                         else
2110                                 sc->bnx_phyno = f + 1;
2111                 } else {
2112                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2113                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2114                                 sc->bnx_phyno = f + 8;
2115                         else
2116                                 sc->bnx_phyno = f + 1;
2117                 }
2118         }
2119
2120         if (sc->bnx_flags & BNX_FLAG_TBI) {
2121                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2122                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2123                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2124                 ifmedia_add(&sc->bnx_ifmedia,
2125                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2126                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2127                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2128                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2129         } else {
2130                 struct mii_probe_args mii_args;
2131
2132                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2133                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2134                 mii_args.mii_capmask = capmask;
2135                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2136                 mii_args.mii_priv = mii_priv;
2137
2138                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2139                 if (error) {
2140                         device_printf(dev, "MII without any PHY!\n");
2141                         goto fail;
2142                 }
2143         }
2144
2145         /*
2146          * Create sysctl nodes.
2147          */
2148         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2149         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2150                                               SYSCTL_STATIC_CHILDREN(_hw),
2151                                               OID_AUTO,
2152                                               device_get_nameunit(dev),
2153                                               CTLFLAG_RD, 0, "");
2154         if (sc->bnx_sysctl_tree == NULL) {
2155                 device_printf(dev, "can't add sysctl node\n");
2156                 error = ENXIO;
2157                 goto fail;
2158         }
2159
2160         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2161                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2162                         OID_AUTO, "rx_coal_ticks",
2163                         CTLTYPE_INT | CTLFLAG_RW,
2164                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2165                         "Receive coalescing ticks (usec).");
2166         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2167                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2168                         OID_AUTO, "tx_coal_ticks",
2169                         CTLTYPE_INT | CTLFLAG_RW,
2170                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2171                         "Transmit coalescing ticks (usec).");
2172         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2173                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2174                         OID_AUTO, "rx_coal_bds",
2175                         CTLTYPE_INT | CTLFLAG_RW,
2176                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2177                         "Receive max coalesced BD count.");
2178         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2179                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2180                         OID_AUTO, "tx_coal_bds",
2181                         CTLTYPE_INT | CTLFLAG_RW,
2182                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2183                         "Transmit max coalesced BD count.");
2184         /*
2185          * A common design characteristic for many Broadcom
2186          * client controllers is that they only support a
2187          * single outstanding DMA read operation on the PCIe
2188          * bus. This means that it will take twice as long to
2189          * fetch a TX frame that is split into header and
2190          * payload buffers as it does to fetch a single,
2191          * contiguous TX frame (2 reads vs. 1 read). For these
2192          * controllers, coalescing buffers to reduce the number
2193          * of memory reads is effective way to get maximum
2194          * performance(about 940Mbps).  Without collapsing TX
2195          * buffers the maximum TCP bulk transfer performance
2196          * is about 850Mbps. However forcing coalescing mbufs
2197          * consumes a lot of CPU cycles, so leave it off by
2198          * default.
2199          */
2200         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2201             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2202             "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2203             "Force defragment on TX path");
2204
2205         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2206             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2207             "tx_wreg", CTLFLAG_RW, &sc->bnx_tx_wreg, 0,
2208             "# of segments before writing to hardware register");
2209
2210         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2211             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2212             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2213             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2214             "Receive max coalesced BD count during interrupt.");
2215         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2216             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2217             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2218             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2219             "Transmit max coalesced BD count during interrupt.");
2220
2221 #ifdef BNX_TSO_DEBUG
2222         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2223                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2224                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2225                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2226                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2227         }
2228 #endif
2229
2230         /*
2231          * Call MI attach routine.
2232          */
2233         ether_ifattach(ifp, ether_addr, NULL);
2234
2235         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2236
2237 #ifdef IFPOLL_ENABLE
2238         ifpoll_compat_setup(&sc->bnx_npoll,
2239             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2240             device_get_unit(dev), ifp->if_serializer);
2241 #endif
2242
2243         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2244                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2245                         intr_func = bnx_msi_oneshot;
2246                         if (bootverbose)
2247                                 device_printf(dev, "oneshot MSI\n");
2248                 } else {
2249                         intr_func = bnx_msi;
2250                 }
2251         } else {
2252                 intr_func = bnx_intr_legacy;
2253         }
2254         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2255             &sc->bnx_intrhand, ifp->if_serializer);
2256         if (error) {
2257                 ether_ifdetach(ifp);
2258                 device_printf(dev, "couldn't set up irq\n");
2259                 goto fail;
2260         }
2261
2262         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2263         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2264
2265         return(0);
2266 fail:
2267         bnx_detach(dev);
2268         return(error);
2269 }
2270
2271 static int
2272 bnx_detach(device_t dev)
2273 {
2274         struct bnx_softc *sc = device_get_softc(dev);
2275
2276         if (device_is_attached(dev)) {
2277                 struct ifnet *ifp = &sc->arpcom.ac_if;
2278
2279                 lwkt_serialize_enter(ifp->if_serializer);
2280                 bnx_stop(sc);
2281                 bnx_reset(sc);
2282                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2283                 lwkt_serialize_exit(ifp->if_serializer);
2284
2285                 ether_ifdetach(ifp);
2286         }
2287
2288         if (sc->bnx_flags & BNX_FLAG_TBI)
2289                 ifmedia_removeall(&sc->bnx_ifmedia);
2290         if (sc->bnx_miibus)
2291                 device_delete_child(dev, sc->bnx_miibus);
2292         bus_generic_detach(dev);
2293
2294         if (sc->bnx_irq != NULL) {
2295                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2296                     sc->bnx_irq);
2297         }
2298         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2299                 pci_release_msi(dev);
2300
2301         if (sc->bnx_res != NULL) {
2302                 bus_release_resource(dev, SYS_RES_MEMORY,
2303                     BGE_PCI_BAR0, sc->bnx_res);
2304         }
2305
2306         if (sc->bnx_sysctl_tree != NULL)
2307                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2308
2309         bnx_dma_free(sc);
2310
2311         return 0;
2312 }
2313
2314 static void
2315 bnx_reset(struct bnx_softc *sc)
2316 {
2317         device_t dev;
2318         uint32_t cachesize, command, pcistate, reset;
2319         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2320         int i, val = 0;
2321         uint16_t devctl;
2322
2323         dev = sc->bnx_dev;
2324
2325         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
2326                 write_op = bnx_writemem_direct;
2327         else
2328                 write_op = bnx_writereg_ind;
2329
2330         /* Save some important PCI state. */
2331         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2332         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2333         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2334
2335         pci_write_config(dev, BGE_PCI_MISC_CTL,
2336             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2337             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2338             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2339
2340         /* Disable fastboot on controllers that support it. */
2341         if (bootverbose)
2342                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2343         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2344
2345         /*
2346          * Write the magic number to SRAM at offset 0xB50.
2347          * When firmware finishes its initialization it will
2348          * write ~BGE_MAGIC_NUMBER to the same location.
2349          */
2350         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2351
2352         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2353
2354         /* XXX: Broadcom Linux driver. */
2355         /* Force PCI-E 1.0a mode */
2356         if (!BNX_IS_57765_PLUS(sc) &&
2357             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2358             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2359              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2360                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2361                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2362         }
2363         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2364                 /* Prevent PCIE link training during global reset */
2365                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2366                 reset |= (1<<29);
2367         }
2368
2369         /*
2370          * Set GPHY Power Down Override to leave GPHY
2371          * powered up in D0 uninitialized.
2372          */
2373         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2374                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2375
2376         /* Issue global reset */
2377         write_op(sc, BGE_MISC_CFG, reset);
2378
2379         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2380                 uint32_t status, ctrl;
2381
2382                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2383                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2384                     status | BGE_VCPU_STATUS_DRV_RESET);
2385                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2386                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2387                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2388         }
2389
2390         DELAY(1000);
2391
2392         /* XXX: Broadcom Linux driver. */
2393         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2394                 uint32_t v;
2395
2396                 DELAY(500000); /* wait for link training to complete */
2397                 v = pci_read_config(dev, 0xc4, 4);
2398                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2399         }
2400
2401         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2402
2403         /* Disable no snoop and disable relaxed ordering. */
2404         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2405
2406         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2407         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2408                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2409                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2410         }
2411
2412         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2413             devctl, 2);
2414
2415         /* Clear error status. */
2416         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2417             PCIEM_DEVSTS_CORR_ERR |
2418             PCIEM_DEVSTS_NFATAL_ERR |
2419             PCIEM_DEVSTS_FATAL_ERR |
2420             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2421
2422         /* Reset some of the PCI state that got zapped by reset */
2423         pci_write_config(dev, BGE_PCI_MISC_CTL,
2424             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2425             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2426             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2427         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2428         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2429         write_op(sc, BGE_MISC_CFG, (65 << 1));
2430
2431         /* Enable memory arbiter */
2432         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2433
2434         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2435                 for (i = 0; i < BNX_TIMEOUT; i++) {
2436                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2437                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2438                                 break;
2439                         DELAY(100);
2440                 }
2441                 if (i == BNX_TIMEOUT) {
2442                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2443                         return;
2444                 }
2445         } else {
2446                 /*
2447                  * Poll until we see the 1's complement of the magic number.
2448                  * This indicates that the firmware initialization
2449                  * is complete.
2450                  */
2451                 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2452                         val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2453                         if (val == ~BGE_MAGIC_NUMBER)
2454                                 break;
2455                         DELAY(10);
2456                 }
2457                 if (i == BNX_FIRMWARE_TIMEOUT) {
2458                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2459                                   "timed out, found 0x%08x\n", val);
2460                 }
2461
2462                 /* BCM57765 A0 needs additional time before accessing. */
2463                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2464                         DELAY(10 * 1000);
2465         }
2466
2467         /*
2468          * XXX Wait for the value of the PCISTATE register to
2469          * return to its original pre-reset state. This is a
2470          * fairly good indicator of reset completion. If we don't
2471          * wait for the reset to fully complete, trying to read
2472          * from the device's non-PCI registers may yield garbage
2473          * results.
2474          */
2475         for (i = 0; i < BNX_TIMEOUT; i++) {
2476                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2477                         break;
2478                 DELAY(10);
2479         }
2480
2481         /* Fix up byte swapping */
2482         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2483
2484         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2485
2486         /*
2487          * The 5704 in TBI mode apparently needs some special
2488          * adjustment to insure the SERDES drive level is set
2489          * to 1.2V.
2490          */
2491         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2492             (sc->bnx_flags & BNX_FLAG_TBI)) {
2493                 uint32_t serdescfg;
2494
2495                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2496                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2497                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2498         }
2499
2500         CSR_WRITE_4(sc, BGE_MI_MODE,
2501             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2502         DELAY(80);
2503
2504         /* XXX: Broadcom Linux driver. */
2505         if (!BNX_IS_57765_PLUS(sc)) {
2506                 uint32_t v;
2507
2508                 /* Enable Data FIFO protection. */
2509                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2510                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2511         }
2512
2513         DELAY(10000);
2514
2515         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2516                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2517                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2518         }
2519 }
2520
2521 /*
2522  * Frame reception handling. This is called if there's a frame
2523  * on the receive return list.
2524  *
2525  * Note: we have to be able to handle two possibilities here:
2526  * 1) the frame is from the jumbo recieve ring
2527  * 2) the frame is from the standard receive ring
2528  */
2529
2530 static void
2531 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod, int count)
2532 {
2533         struct ifnet *ifp;
2534         int stdcnt = 0, jumbocnt = 0;
2535
2536         ifp = &sc->arpcom.ac_if;
2537
2538         while (sc->bnx_rx_saved_considx != rx_prod && count != 0) {
2539                 struct bge_rx_bd        *cur_rx;
2540                 uint32_t                rxidx;
2541                 struct mbuf             *m = NULL;
2542                 uint16_t                vlan_tag = 0;
2543                 int                     have_tag = 0;
2544
2545                 --count;
2546
2547                 cur_rx =
2548             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2549
2550                 rxidx = cur_rx->bge_idx;
2551                 BNX_INC(sc->bnx_rx_saved_considx, sc->bnx_return_ring_cnt);
2552
2553                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2554                         have_tag = 1;
2555                         vlan_tag = cur_rx->bge_vlan_tag;
2556                 }
2557
2558                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2559                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2560                         jumbocnt++;
2561
2562                         if (rxidx != sc->bnx_jumbo) {
2563                                 IFNET_STAT_INC(ifp, ierrors, 1);
2564                                 if_printf(ifp, "sw jumbo index(%d) "
2565                                     "and hw jumbo index(%d) mismatch, drop!\n",
2566                                     sc->bnx_jumbo, rxidx);
2567                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2568                                 continue;
2569                         }
2570
2571                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2572                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2573                                 IFNET_STAT_INC(ifp, ierrors, 1);
2574                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2575                                 continue;
2576                         }
2577                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2578                                 IFNET_STAT_INC(ifp, ierrors, 1);
2579                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2580                                 continue;
2581                         }
2582                 } else {
2583                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2584                         stdcnt++;
2585
2586                         if (rxidx != sc->bnx_std) {
2587                                 IFNET_STAT_INC(ifp, ierrors, 1);
2588                                 if_printf(ifp, "sw std index(%d) "
2589                                     "and hw std index(%d) mismatch, drop!\n",
2590                                     sc->bnx_std, rxidx);
2591                                 bnx_setup_rxdesc_std(sc, rxidx);
2592                                 continue;
2593                         }
2594
2595                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2596                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2597                                 IFNET_STAT_INC(ifp, ierrors, 1);
2598                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2599                                 continue;
2600                         }
2601                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2602                                 IFNET_STAT_INC(ifp, ierrors, 1);
2603                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2604                                 continue;
2605                         }
2606                 }
2607
2608                 IFNET_STAT_INC(ifp, ipackets, 1);
2609                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2610                 m->m_pkthdr.rcvif = ifp;
2611
2612                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2613                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2614                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2615                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2616                                 if ((cur_rx->bge_error_flag &
2617                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2618                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2619                         }
2620                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2621                                 m->m_pkthdr.csum_data =
2622                                     cur_rx->bge_tcp_udp_csum;
2623                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2624                                     CSUM_PSEUDO_HDR;
2625                         }
2626                 }
2627
2628                 /*
2629                  * If we received a packet with a vlan tag, pass it
2630                  * to vlan_input() instead of ether_input().
2631                  */
2632                 if (have_tag) {
2633                         m->m_flags |= M_VLANTAG;
2634                         m->m_pkthdr.ether_vlantag = vlan_tag;
2635                 }
2636                 ifp->if_input(ifp, m);
2637         }
2638
2639         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2640         if (stdcnt)
2641                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2642         if (jumbocnt)
2643                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2644 }
2645
2646 static void
2647 bnx_txeof(struct bnx_softc *sc, uint16_t tx_cons)
2648 {
2649         struct ifnet *ifp;
2650
2651         ifp = &sc->arpcom.ac_if;
2652
2653         /*
2654          * Go through our tx ring and free mbufs for those
2655          * frames that have been sent.
2656          */
2657         while (sc->bnx_tx_saved_considx != tx_cons) {
2658                 uint32_t idx = 0;
2659
2660                 idx = sc->bnx_tx_saved_considx;
2661                 if (sc->bnx_cdata.bnx_tx_chain[idx] != NULL) {
2662                         IFNET_STAT_INC(ifp, opackets, 1);
2663                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
2664                             sc->bnx_cdata.bnx_tx_dmamap[idx]);
2665                         m_freem(sc->bnx_cdata.bnx_tx_chain[idx]);
2666                         sc->bnx_cdata.bnx_tx_chain[idx] = NULL;
2667                 }
2668                 sc->bnx_txcnt--;
2669                 BNX_INC(sc->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2670         }
2671
2672         if ((BGE_TX_RING_CNT - sc->bnx_txcnt) >=
2673             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2674                 ifq_clr_oactive(&ifp->if_snd);
2675
2676         if (sc->bnx_txcnt == 0)
2677                 ifp->if_timer = 0;
2678
2679         if (!ifq_is_empty(&ifp->if_snd))
2680                 if_devstart(ifp);
2681 }
2682
2683 #ifdef IFPOLL_ENABLE
2684
2685 static void
2686 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2687 {
2688         struct bnx_softc *sc = ifp->if_softc;
2689
2690         ASSERT_SERIALIZED(ifp->if_serializer);
2691
2692         if (info != NULL) {
2693                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2694
2695                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2696                 info->ifpi_rx[cpuid].arg = NULL;
2697                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2698
2699                 if (ifp->if_flags & IFF_RUNNING)
2700                         bnx_disable_intr(sc);
2701                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2702         } else {
2703                 if (ifp->if_flags & IFF_RUNNING)
2704                         bnx_enable_intr(sc);
2705                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2706         }
2707 }
2708
2709 static void
2710 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2711 {
2712         struct bnx_softc *sc = ifp->if_softc;
2713         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2714         uint16_t rx_prod, tx_cons;
2715
2716         ASSERT_SERIALIZED(ifp->if_serializer);
2717
2718         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2719                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2720                 /*
2721                  * Process link state changes.
2722                  */
2723                 bnx_link_poll(sc);
2724         }
2725
2726         sc->bnx_status_tag = sblk->bge_status_tag;
2727
2728         /*
2729          * Use a load fence to ensure that status_tag is saved
2730          * before rx_prod and tx_cons.
2731          */
2732         cpu_lfence();
2733
2734         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2735         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2736
2737         if (sc->bnx_rx_saved_considx != rx_prod)
2738                 bnx_rxeof(sc, rx_prod, cycle);
2739
2740         if (sc->bnx_tx_saved_considx != tx_cons)
2741                 bnx_txeof(sc, tx_cons);
2742
2743         if (sc->bnx_coal_chg)
2744                 bnx_coal_change(sc);
2745 }
2746
2747 #endif  /* IFPOLL_ENABLE */
2748
2749 static void
2750 bnx_intr_legacy(void *xsc)
2751 {
2752         struct bnx_softc *sc = xsc;
2753         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2754
2755         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2756                 uint32_t val;
2757
2758                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2759                 if (val & BGE_PCISTAT_INTR_NOTACT)
2760                         return;
2761         }
2762
2763         /*
2764          * NOTE:
2765          * Interrupt will have to be disabled if tagged status
2766          * is used, else interrupt will always be asserted on
2767          * certain chips (at least on BCM5750 AX/BX).
2768          */
2769         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2770
2771         bnx_intr(sc);
2772 }
2773
2774 static void
2775 bnx_msi(void *xsc)
2776 {
2777         struct bnx_softc *sc = xsc;
2778
2779         /* Disable interrupt first */
2780         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2781         bnx_intr(sc);
2782 }
2783
2784 static void
2785 bnx_msi_oneshot(void *xsc)
2786 {
2787         bnx_intr(xsc);
2788 }
2789
2790 static void
2791 bnx_intr(struct bnx_softc *sc)
2792 {
2793         struct ifnet *ifp = &sc->arpcom.ac_if;
2794         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2795         uint16_t rx_prod, tx_cons;
2796         uint32_t status;
2797
2798         sc->bnx_status_tag = sblk->bge_status_tag;
2799         /*
2800          * Use a load fence to ensure that status_tag is saved
2801          * before rx_prod, tx_cons and status.
2802          */
2803         cpu_lfence();
2804
2805         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2806         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2807         status = sblk->bge_status;
2808
2809         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2810                 bnx_link_poll(sc);
2811
2812         if (ifp->if_flags & IFF_RUNNING) {
2813                 if (sc->bnx_rx_saved_considx != rx_prod)
2814                         bnx_rxeof(sc, rx_prod, -1);
2815
2816                 if (sc->bnx_tx_saved_considx != tx_cons)
2817                         bnx_txeof(sc, tx_cons);
2818         }
2819
2820         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2821
2822         if (sc->bnx_coal_chg)
2823                 bnx_coal_change(sc);
2824 }
2825
2826 static void
2827 bnx_tick(void *xsc)
2828 {
2829         struct bnx_softc *sc = xsc;
2830         struct ifnet *ifp = &sc->arpcom.ac_if;
2831
2832         lwkt_serialize_enter(ifp->if_serializer);
2833
2834         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2835
2836         bnx_stats_update_regs(sc);
2837
2838         if (sc->bnx_flags & BNX_FLAG_TBI) {
2839                 /*
2840                  * Since in TBI mode auto-polling can't be used we should poll
2841                  * link status manually. Here we register pending link event
2842                  * and trigger interrupt.
2843                  */
2844                 sc->bnx_link_evt++;
2845                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2846         } else if (!sc->bnx_link) {
2847                 mii_tick(device_get_softc(sc->bnx_miibus));
2848         }
2849
2850         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2851
2852         lwkt_serialize_exit(ifp->if_serializer);
2853 }
2854
2855 static void
2856 bnx_stats_update_regs(struct bnx_softc *sc)
2857 {
2858         struct ifnet *ifp = &sc->arpcom.ac_if;
2859         struct bge_mac_stats_regs stats;
2860         uint32_t *s;
2861         int i;
2862
2863         s = (uint32_t *)&stats;
2864         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2865                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2866                 s++;
2867         }
2868
2869         IFNET_STAT_SET(ifp, collisions,
2870            (stats.dot3StatsSingleCollisionFrames +
2871            stats.dot3StatsMultipleCollisionFrames +
2872            stats.dot3StatsExcessiveCollisions +
2873            stats.dot3StatsLateCollisions));
2874 }
2875
2876 /*
2877  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2878  * pointers to descriptors.
2879  */
2880 static int
2881 bnx_encap(struct bnx_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
2882     int *segs_used)
2883 {
2884         struct bge_tx_bd *d = NULL;
2885         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2886         bus_dma_segment_t segs[BNX_NSEG_NEW];
2887         bus_dmamap_t map;
2888         int error, maxsegs, nsegs, idx, i;
2889         struct mbuf *m_head = *m_head0, *m_new;
2890
2891         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2892 #ifdef BNX_TSO_DEBUG
2893                 int tso_nsegs;
2894 #endif
2895
2896                 error = bnx_setup_tso(sc, m_head0, &mss, &csum_flags);
2897                 if (error)
2898                         return error;
2899                 m_head = *m_head0;
2900
2901 #ifdef BNX_TSO_DEBUG
2902                 tso_nsegs = (m_head->m_pkthdr.len /
2903                     m_head->m_pkthdr.tso_segsz) - 1;
2904                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2905                         tso_nsegs = BNX_TSO_NSTATS - 1;
2906                 else if (tso_nsegs < 0)
2907                         tso_nsegs = 0;
2908                 sc->bnx_tsosegs[tso_nsegs]++;
2909 #endif
2910         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2911                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2912                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2913                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2914                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2915                 if (m_head->m_flags & M_LASTFRAG)
2916                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2917                 else if (m_head->m_flags & M_FRAG)
2918                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2919         }
2920         if (m_head->m_flags & M_VLANTAG) {
2921                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2922                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2923         }
2924
2925         idx = *txidx;
2926         map = sc->bnx_cdata.bnx_tx_dmamap[idx];
2927
2928         maxsegs = (BGE_TX_RING_CNT - sc->bnx_txcnt) - BNX_NSEG_RSVD;
2929         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2930                 ("not enough segments %d", maxsegs));
2931
2932         if (maxsegs > BNX_NSEG_NEW)
2933                 maxsegs = BNX_NSEG_NEW;
2934
2935         /*
2936          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2937          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2938          * but when such padded frames employ the bge IP/TCP checksum
2939          * offload, the hardware checksum assist gives incorrect results
2940          * (possibly from incorporating its own padding into the UDP/TCP
2941          * checksum; who knows).  If we pad such runts with zeros, the
2942          * onboard checksum comes out correct.
2943          */
2944         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2945             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2946                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2947                 if (error)
2948                         goto back;
2949         }
2950
2951         if ((sc->bnx_flags & BNX_FLAG_SHORTDMA) && m_head->m_next != NULL) {
2952                 m_new = bnx_defrag_shortdma(m_head);
2953                 if (m_new == NULL) {
2954                         error = ENOBUFS;
2955                         goto back;
2956                 }
2957                 *m_head0 = m_head = m_new;
2958         }
2959         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2960             sc->bnx_force_defrag && m_head->m_next != NULL) {
2961                 /*
2962                  * Forcefully defragment mbuf chain to overcome hardware
2963                  * limitation which only support a single outstanding
2964                  * DMA read operation.  If it fails, keep moving on using
2965                  * the original mbuf chain.
2966                  */
2967                 m_new = m_defrag(m_head, MB_DONTWAIT);
2968                 if (m_new != NULL)
2969                         *m_head0 = m_head = m_new;
2970         }
2971
2972         error = bus_dmamap_load_mbuf_defrag(sc->bnx_cdata.bnx_tx_mtag, map,
2973                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2974         if (error)
2975                 goto back;
2976         *segs_used += nsegs;
2977
2978         m_head = *m_head0;
2979         bus_dmamap_sync(sc->bnx_cdata.bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2980
2981         for (i = 0; ; i++) {
2982                 d = &sc->bnx_ldata.bnx_tx_ring[idx];
2983
2984                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2985                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2986                 d->bge_len = segs[i].ds_len;
2987                 d->bge_flags = csum_flags;
2988                 d->bge_vlan_tag = vlan_tag;
2989                 d->bge_mss = mss;
2990
2991                 if (i == nsegs - 1)
2992                         break;
2993                 BNX_INC(idx, BGE_TX_RING_CNT);
2994         }
2995         /* Mark the last segment as end of packet... */
2996         d->bge_flags |= BGE_TXBDFLAG_END;
2997
2998         /*
2999          * Insure that the map for this transmission is placed at
3000          * the array index of the last descriptor in this chain.
3001          */
3002         sc->bnx_cdata.bnx_tx_dmamap[*txidx] = sc->bnx_cdata.bnx_tx_dmamap[idx];
3003         sc->bnx_cdata.bnx_tx_dmamap[idx] = map;
3004         sc->bnx_cdata.bnx_tx_chain[idx] = m_head;
3005         sc->bnx_txcnt += nsegs;
3006
3007         BNX_INC(idx, BGE_TX_RING_CNT);
3008         *txidx = idx;
3009 back:
3010         if (error) {
3011                 m_freem(*m_head0);
3012                 *m_head0 = NULL;
3013         }
3014         return error;
3015 }
3016
3017 /*
3018  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3019  * to the mbuf data regions directly in the transmit descriptors.
3020  */
3021 static void
3022 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3023 {
3024         struct bnx_softc *sc = ifp->if_softc;
3025         struct mbuf *m_head = NULL;
3026         uint32_t prodidx;
3027         int nsegs = 0;
3028
3029         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
3030
3031         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
3032                 return;
3033
3034         prodidx = sc->bnx_tx_prodidx;
3035
3036         while (sc->bnx_cdata.bnx_tx_chain[prodidx] == NULL) {
3037                 /*
3038                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3039                  * descriptors of the end of the ring.  Also make
3040                  * sure there are BGE_NSEG_SPARE descriptors for
3041                  * jumbo buffers' or TSO segments' defragmentation.
3042                  */
3043                 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
3044                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
3045                         ifq_set_oactive(&ifp->if_snd);
3046                         break;
3047                 }
3048
3049                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3050                 if (m_head == NULL)
3051                         break;
3052
3053                 /*
3054                  * Pack the data into the transmit ring. If we
3055                  * don't have room, set the OACTIVE flag and wait
3056                  * for the NIC to drain the ring.
3057                  */
3058                 if (bnx_encap(sc, &m_head, &prodidx, &nsegs)) {
3059                         ifq_set_oactive(&ifp->if_snd);
3060                         IFNET_STAT_INC(ifp, oerrors, 1);
3061                         break;
3062                 }
3063
3064                 if (nsegs >= sc->bnx_tx_wreg) {
3065                         /* Transmit */
3066                         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3067                         nsegs = 0;
3068                 }
3069
3070                 ETHER_BPF_MTAP(ifp, m_head);
3071
3072                 /*
3073                  * Set a timeout in case the chip goes out to lunch.
3074                  */
3075                 ifp->if_timer = 5;
3076         }
3077
3078         if (nsegs > 0) {
3079                 /* Transmit */
3080                 bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3081         }
3082         sc->bnx_tx_prodidx = prodidx;
3083 }
3084
3085 static void
3086 bnx_init(void *xsc)
3087 {
3088         struct bnx_softc *sc = xsc;
3089         struct ifnet *ifp = &sc->arpcom.ac_if;
3090         uint16_t *m;
3091         uint32_t mode;
3092
3093         ASSERT_SERIALIZED(ifp->if_serializer);
3094
3095         /* Cancel pending I/O and flush buffers. */
3096         bnx_stop(sc);
3097         bnx_reset(sc);
3098         bnx_chipinit(sc);
3099
3100         /*
3101          * Init the various state machines, ring
3102          * control blocks and firmware.
3103          */
3104         if (bnx_blockinit(sc)) {
3105                 if_printf(ifp, "initialization failure\n");
3106                 bnx_stop(sc);
3107                 return;
3108         }
3109
3110         /* Specify MTU. */
3111         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3112             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3113
3114         /* Load our MAC address. */
3115         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3116         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3117         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3118
3119         /* Enable or disable promiscuous mode as needed. */
3120         bnx_setpromisc(sc);
3121
3122         /* Program multicast filter. */
3123         bnx_setmulti(sc);
3124
3125         /* Init RX ring. */
3126         if (bnx_init_rx_ring_std(sc)) {
3127                 if_printf(ifp, "RX ring initialization failed\n");
3128                 bnx_stop(sc);
3129                 return;
3130         }
3131
3132         /* Init jumbo RX ring. */
3133         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3134                 if (bnx_init_rx_ring_jumbo(sc)) {
3135                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3136                         bnx_stop(sc);
3137                         return;
3138                 }
3139         }
3140
3141         /* Init our RX return ring index */
3142         sc->bnx_rx_saved_considx = 0;
3143
3144         /* Init TX ring. */
3145         bnx_init_tx_ring(sc);
3146
3147         /* Enable TX MAC state machine lockup fix. */
3148         mode = CSR_READ_4(sc, BGE_TX_MODE);
3149         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3150         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3151             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3152                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3153                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3154                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3155         }
3156         /* Turn on transmitter */
3157         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3158
3159         /* Turn on receiver */
3160         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3161
3162         /*
3163          * Set the number of good frames to receive after RX MBUF
3164          * Low Watermark has been reached.  After the RX MAC receives
3165          * this number of frames, it will drop subsequent incoming
3166          * frames until the MBUF High Watermark is reached.
3167          */
3168         if (BNX_IS_57765_FAMILY(sc))
3169                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3170         else
3171                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3172
3173         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3174                 if (bootverbose) {
3175                         if_printf(ifp, "MSI_MODE: %#x\n",
3176                             CSR_READ_4(sc, BGE_MSI_MODE));
3177                 }
3178         }
3179
3180         /* Tell firmware we're alive. */
3181         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3182
3183         /* Enable host interrupts if polling(4) is not enabled. */
3184         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3185 #ifdef IFPOLL_ENABLE
3186         if (ifp->if_flags & IFF_NPOLLING)
3187                 bnx_disable_intr(sc);
3188         else
3189 #endif
3190         bnx_enable_intr(sc);
3191
3192         bnx_ifmedia_upd(ifp);
3193
3194         ifp->if_flags |= IFF_RUNNING;
3195         ifq_clr_oactive(&ifp->if_snd);
3196
3197         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3198             sc->bnx_stat_cpuid);
3199 }
3200
3201 /*
3202  * Set media options.
3203  */
3204 static int
3205 bnx_ifmedia_upd(struct ifnet *ifp)
3206 {
3207         struct bnx_softc *sc = ifp->if_softc;
3208
3209         /* If this is a 1000baseX NIC, enable the TBI port. */
3210         if (sc->bnx_flags & BNX_FLAG_TBI) {
3211                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3212
3213                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3214                         return(EINVAL);
3215
3216                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3217                 case IFM_AUTO:
3218                         break;
3219
3220                 case IFM_1000_SX:
3221                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3222                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3223                                     BGE_MACMODE_HALF_DUPLEX);
3224                         } else {
3225                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3226                                     BGE_MACMODE_HALF_DUPLEX);
3227                         }
3228                         break;
3229                 default:
3230                         return(EINVAL);
3231                 }
3232         } else {
3233                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3234
3235                 sc->bnx_link_evt++;
3236                 sc->bnx_link = 0;
3237                 if (mii->mii_instance) {
3238                         struct mii_softc *miisc;
3239
3240                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3241                                 mii_phy_reset(miisc);
3242                 }
3243                 mii_mediachg(mii);
3244
3245                 /*
3246                  * Force an interrupt so that we will call bnx_link_upd
3247                  * if needed and clear any pending link state attention.
3248                  * Without this we are not getting any further interrupts
3249                  * for link state changes and thus will not UP the link and
3250                  * not be able to send in bnx_start.  The only way to get
3251                  * things working was to receive a packet and get an RX
3252                  * intr.
3253                  *
3254                  * bnx_tick should help for fiber cards and we might not
3255                  * need to do this here if BNX_FLAG_TBI is set but as
3256                  * we poll for fiber anyway it should not harm.
3257                  */
3258                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3259         }
3260         return(0);
3261 }
3262
3263 /*
3264  * Report current media status.
3265  */
3266 static void
3267 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3268 {
3269         struct bnx_softc *sc = ifp->if_softc;
3270
3271         if (sc->bnx_flags & BNX_FLAG_TBI) {
3272                 ifmr->ifm_status = IFM_AVALID;
3273                 ifmr->ifm_active = IFM_ETHER;
3274                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3275                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3276                         ifmr->ifm_status |= IFM_ACTIVE;
3277                 } else {
3278                         ifmr->ifm_active |= IFM_NONE;
3279                         return;
3280                 }
3281
3282                 ifmr->ifm_active |= IFM_1000_SX;
3283                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3284                         ifmr->ifm_active |= IFM_HDX;
3285                 else
3286                         ifmr->ifm_active |= IFM_FDX;
3287         } else {
3288                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3289
3290                 mii_pollstat(mii);
3291                 ifmr->ifm_active = mii->mii_media_active;
3292                 ifmr->ifm_status = mii->mii_media_status;
3293         }
3294 }
3295
3296 static int
3297 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3298 {
3299         struct bnx_softc *sc = ifp->if_softc;
3300         struct ifreq *ifr = (struct ifreq *)data;
3301         int mask, error = 0;
3302
3303         ASSERT_SERIALIZED(ifp->if_serializer);
3304
3305         switch (command) {
3306         case SIOCSIFMTU:
3307                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3308                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3309                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3310                         error = EINVAL;
3311                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3312                         ifp->if_mtu = ifr->ifr_mtu;
3313                         if (ifp->if_flags & IFF_RUNNING)
3314                                 bnx_init(sc);
3315                 }
3316                 break;
3317         case SIOCSIFFLAGS:
3318                 if (ifp->if_flags & IFF_UP) {
3319                         if (ifp->if_flags & IFF_RUNNING) {
3320                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3321
3322                                 /*
3323                                  * If only the state of the PROMISC flag
3324                                  * changed, then just use the 'set promisc
3325                                  * mode' command instead of reinitializing
3326                                  * the entire NIC. Doing a full re-init
3327                                  * means reloading the firmware and waiting
3328                                  * for it to start up, which may take a
3329                                  * second or two.  Similarly for ALLMULTI.
3330                                  */
3331                                 if (mask & IFF_PROMISC)
3332                                         bnx_setpromisc(sc);
3333                                 if (mask & IFF_ALLMULTI)
3334                                         bnx_setmulti(sc);
3335                         } else {
3336                                 bnx_init(sc);
3337                         }
3338                 } else if (ifp->if_flags & IFF_RUNNING) {
3339                         bnx_stop(sc);
3340                 }
3341                 sc->bnx_if_flags = ifp->if_flags;
3342                 break;
3343         case SIOCADDMULTI:
3344         case SIOCDELMULTI:
3345                 if (ifp->if_flags & IFF_RUNNING)
3346                         bnx_setmulti(sc);
3347                 break;
3348         case SIOCSIFMEDIA:
3349         case SIOCGIFMEDIA:
3350                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3351                         error = ifmedia_ioctl(ifp, ifr,
3352                             &sc->bnx_ifmedia, command);
3353                 } else {
3354                         struct mii_data *mii;
3355
3356                         mii = device_get_softc(sc->bnx_miibus);
3357                         error = ifmedia_ioctl(ifp, ifr,
3358                                               &mii->mii_media, command);
3359                 }
3360                 break;
3361         case SIOCSIFCAP:
3362                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3363                 if (mask & IFCAP_HWCSUM) {
3364                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3365                         if (ifp->if_capenable & IFCAP_TXCSUM)
3366                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3367                         else
3368                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3369                 }
3370                 if (mask & IFCAP_TSO) {
3371                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3372                         if (ifp->if_capenable & IFCAP_TSO)
3373                                 ifp->if_hwassist |= CSUM_TSO;
3374                         else
3375                                 ifp->if_hwassist &= ~CSUM_TSO;
3376                 }
3377                 break;
3378         default:
3379                 error = ether_ioctl(ifp, command, data);
3380                 break;
3381         }
3382         return error;
3383 }
3384
3385 static void
3386 bnx_watchdog(struct ifnet *ifp)
3387 {
3388         struct bnx_softc *sc = ifp->if_softc;
3389
3390         if_printf(ifp, "watchdog timeout -- resetting\n");
3391
3392         bnx_init(sc);
3393
3394         IFNET_STAT_INC(ifp, oerrors, 1);
3395
3396         if (!ifq_is_empty(&ifp->if_snd))
3397                 if_devstart(ifp);
3398 }
3399
3400 /*
3401  * Stop the adapter and free any mbufs allocated to the
3402  * RX and TX lists.
3403  */
3404 static void
3405 bnx_stop(struct bnx_softc *sc)
3406 {
3407         struct ifnet *ifp = &sc->arpcom.ac_if;
3408
3409         ASSERT_SERIALIZED(ifp->if_serializer);
3410
3411         callout_stop(&sc->bnx_stat_timer);
3412
3413         /*
3414          * Disable all of the receiver blocks
3415          */
3416         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3417         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3418         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3419         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3420         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3421         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3422
3423         /*
3424          * Disable all of the transmit blocks
3425          */
3426         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3427         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3428         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3429         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3430         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3431         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3432
3433         /*
3434          * Shut down all of the memory managers and related
3435          * state machines.
3436          */
3437         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3438         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3439         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3440         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3441
3442         /* Disable host interrupts. */
3443         bnx_disable_intr(sc);
3444
3445         /*
3446          * Tell firmware we're shutting down.
3447          */
3448         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3449
3450         /* Free the RX lists. */
3451         bnx_free_rx_ring_std(sc);
3452
3453         /* Free jumbo RX list. */
3454         if (BNX_IS_JUMBO_CAPABLE(sc))
3455                 bnx_free_rx_ring_jumbo(sc);
3456
3457         /* Free TX buffers. */
3458         bnx_free_tx_ring(sc);
3459
3460         sc->bnx_status_tag = 0;
3461         sc->bnx_link = 0;
3462         sc->bnx_coal_chg = 0;
3463
3464         sc->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
3465
3466         ifp->if_flags &= ~IFF_RUNNING;
3467         ifq_clr_oactive(&ifp->if_snd);
3468         ifp->if_timer = 0;
3469 }
3470
3471 /*
3472  * Stop all chip I/O so that the kernel's probe routines don't
3473  * get confused by errant DMAs when rebooting.
3474  */
3475 static void
3476 bnx_shutdown(device_t dev)
3477 {
3478         struct bnx_softc *sc = device_get_softc(dev);
3479         struct ifnet *ifp = &sc->arpcom.ac_if;
3480
3481         lwkt_serialize_enter(ifp->if_serializer);
3482         bnx_stop(sc);
3483         bnx_reset(sc);
3484         lwkt_serialize_exit(ifp->if_serializer);
3485 }
3486
3487 static int
3488 bnx_suspend(device_t dev)
3489 {
3490         struct bnx_softc *sc = device_get_softc(dev);
3491         struct ifnet *ifp = &sc->arpcom.ac_if;
3492
3493         lwkt_serialize_enter(ifp->if_serializer);
3494         bnx_stop(sc);
3495         lwkt_serialize_exit(ifp->if_serializer);
3496
3497         return 0;
3498 }
3499
3500 static int
3501 bnx_resume(device_t dev)
3502 {
3503         struct bnx_softc *sc = device_get_softc(dev);
3504         struct ifnet *ifp = &sc->arpcom.ac_if;
3505
3506         lwkt_serialize_enter(ifp->if_serializer);
3507
3508         if (ifp->if_flags & IFF_UP) {
3509                 bnx_init(sc);
3510
3511                 if (!ifq_is_empty(&ifp->if_snd))
3512                         if_devstart(ifp);
3513         }
3514
3515         lwkt_serialize_exit(ifp->if_serializer);
3516
3517         return 0;
3518 }
3519
3520 static void
3521 bnx_setpromisc(struct bnx_softc *sc)
3522 {
3523         struct ifnet *ifp = &sc->arpcom.ac_if;
3524
3525         if (ifp->if_flags & IFF_PROMISC)
3526                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3527         else
3528                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3529 }
3530
3531 static void
3532 bnx_dma_free(struct bnx_softc *sc)
3533 {
3534         int i;
3535
3536         /* Destroy RX mbuf DMA stuffs. */
3537         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3538                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3539                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3540                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3541                 }
3542                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3543                                    sc->bnx_cdata.bnx_rx_tmpmap);
3544                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3545         }
3546
3547         /* Destroy TX mbuf DMA stuffs. */
3548         if (sc->bnx_cdata.bnx_tx_mtag != NULL) {
3549                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3550                         bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3551                             sc->bnx_cdata.bnx_tx_dmamap[i]);
3552                 }
3553                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3554         }
3555
3556         /* Destroy standard RX ring */
3557         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3558                            sc->bnx_cdata.bnx_rx_std_ring_map,
3559                            sc->bnx_ldata.bnx_rx_std_ring);
3560
3561         if (BNX_IS_JUMBO_CAPABLE(sc))
3562                 bnx_free_jumbo_mem(sc);
3563
3564         /* Destroy RX return ring */
3565         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3566                            sc->bnx_cdata.bnx_rx_return_ring_map,
3567                            sc->bnx_ldata.bnx_rx_return_ring);
3568
3569         /* Destroy TX ring */
3570         bnx_dma_block_free(sc->bnx_cdata.bnx_tx_ring_tag,
3571                            sc->bnx_cdata.bnx_tx_ring_map,
3572                            sc->bnx_ldata.bnx_tx_ring);
3573
3574         /* Destroy status block */
3575         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3576                            sc->bnx_cdata.bnx_status_map,
3577                            sc->bnx_ldata.bnx_status_block);
3578
3579         /* Destroy the parent tag */
3580         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3581                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3582 }
3583
3584 static int
3585 bnx_dma_alloc(struct bnx_softc *sc)
3586 {
3587         struct ifnet *ifp = &sc->arpcom.ac_if;
3588         bus_size_t txmaxsz;
3589         int i, error;
3590
3591         /*
3592          * Allocate the parent bus DMA tag appropriate for PCI.
3593          *
3594          * All of the NetExtreme/NetLink controllers have 4GB boundary
3595          * DMA bug.
3596          * Whenever an address crosses a multiple of the 4GB boundary
3597          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3598          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3599          * state machine will lockup and cause the device to hang.
3600          */
3601         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3602                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3603                                    NULL, NULL,
3604                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3605                                    BUS_SPACE_MAXSIZE_32BIT,
3606                                    0, &sc->bnx_cdata.bnx_parent_tag);
3607         if (error) {
3608                 if_printf(ifp, "could not allocate parent dma tag\n");
3609                 return error;
3610         }
3611
3612         /*
3613          * Create DMA tag and maps for RX mbufs.
3614          */
3615         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3616                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3617                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3618                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3619                                    &sc->bnx_cdata.bnx_rx_mtag);
3620         if (error) {
3621                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3622                 return error;
3623         }
3624
3625         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3626                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3627         if (error) {
3628                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3629                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3630                 return error;
3631         }
3632
3633         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3634                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3635                                           BUS_DMA_WAITOK,
3636                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3637                 if (error) {
3638                         int j;
3639
3640                         for (j = 0; j < i; ++j) {
3641                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3642                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3643                         }
3644                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3645                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3646
3647                         if_printf(ifp, "could not create DMA map for RX\n");
3648                         return error;
3649                 }
3650         }
3651
3652         /*
3653          * Create DMA tag and maps for TX mbufs.
3654          */
3655         if (sc->bnx_flags & BNX_FLAG_TSO)
3656                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
3657         else
3658                 txmaxsz = BNX_JUMBO_FRAMELEN;
3659         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3660                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3661                                    NULL, NULL,
3662                                    txmaxsz, BNX_NSEG_NEW, PAGE_SIZE,
3663                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3664                                    BUS_DMA_ONEBPAGE,
3665                                    &sc->bnx_cdata.bnx_tx_mtag);
3666         if (error) {
3667                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3668                 return error;
3669         }
3670
3671         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3672                 error = bus_dmamap_create(sc->bnx_cdata.bnx_tx_mtag,
3673                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3674                                           &sc->bnx_cdata.bnx_tx_dmamap[i]);
3675                 if (error) {
3676                         int j;
3677
3678                         for (j = 0; j < i; ++j) {
3679                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3680                                         sc->bnx_cdata.bnx_tx_dmamap[j]);
3681                         }
3682                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3683                         sc->bnx_cdata.bnx_tx_mtag = NULL;
3684
3685                         if_printf(ifp, "could not create DMA map for TX\n");
3686                         return error;
3687                 }
3688         }
3689
3690         /*
3691          * Create DMA stuffs for standard RX ring.
3692          */
3693         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3694                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3695                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3696                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3697                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3698         if (error) {
3699                 if_printf(ifp, "could not create std RX ring\n");
3700                 return error;
3701         }
3702
3703         /*
3704          * Create jumbo buffer pool.
3705          */
3706         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3707                 error = bnx_alloc_jumbo_mem(sc);
3708                 if (error) {
3709                         if_printf(ifp, "could not create jumbo buffer pool\n");
3710                         return error;
3711                 }
3712         }
3713
3714         /*
3715          * Create DMA stuffs for RX return ring.
3716          */
3717         error = bnx_dma_block_alloc(sc,
3718             BGE_RX_RTN_RING_SZ(sc->bnx_return_ring_cnt),
3719             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3720             &sc->bnx_cdata.bnx_rx_return_ring_map,
3721             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3722             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3723         if (error) {
3724                 if_printf(ifp, "could not create RX ret ring\n");
3725                 return error;
3726         }
3727
3728         /*
3729          * Create DMA stuffs for TX ring.
3730          */
3731         error = bnx_dma_block_alloc(sc, BGE_TX_RING_SZ,
3732                                     &sc->bnx_cdata.bnx_tx_ring_tag,
3733                                     &sc->bnx_cdata.bnx_tx_ring_map,
3734                                     (void *)&sc->bnx_ldata.bnx_tx_ring,
3735                                     &sc->bnx_ldata.bnx_tx_ring_paddr);
3736         if (error) {
3737                 if_printf(ifp, "could not create TX ring\n");
3738                 return error;
3739         }
3740
3741         /*
3742          * Create DMA stuffs for status block.
3743          */
3744         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3745                                     &sc->bnx_cdata.bnx_status_tag,
3746                                     &sc->bnx_cdata.bnx_status_map,
3747                                     (void *)&sc->bnx_ldata.bnx_status_block,
3748                                     &sc->bnx_ldata.bnx_status_block_paddr);
3749         if (error) {
3750                 if_printf(ifp, "could not create status block\n");
3751                 return error;
3752         }
3753
3754         return 0;
3755 }
3756
3757 static int
3758 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3759                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3760 {
3761         bus_dmamem_t dmem;
3762         int error;
3763
3764         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3765                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3766                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3767         if (error)
3768                 return error;
3769
3770         *tag = dmem.dmem_tag;
3771         *map = dmem.dmem_map;
3772         *addr = dmem.dmem_addr;
3773         *paddr = dmem.dmem_busaddr;
3774
3775         return 0;
3776 }
3777
3778 static void
3779 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3780 {
3781         if (tag != NULL) {
3782                 bus_dmamap_unload(tag, map);
3783                 bus_dmamem_free(tag, addr, map);
3784                 bus_dma_tag_destroy(tag);
3785         }
3786 }
3787
3788 static void
3789 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3790 {
3791         struct ifnet *ifp = &sc->arpcom.ac_if;
3792
3793 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3794
3795         /*
3796          * Sometimes PCS encoding errors are detected in
3797          * TBI mode (on fiber NICs), and for some reason
3798          * the chip will signal them as link changes.
3799          * If we get a link change event, but the 'PCS
3800          * encoding error' bit in the MAC status register
3801          * is set, don't bother doing a link check.
3802          * This avoids spurious "gigabit link up" messages
3803          * that sometimes appear on fiber NICs during
3804          * periods of heavy traffic.
3805          */
3806         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3807                 if (!sc->bnx_link) {
3808                         sc->bnx_link++;
3809                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3810                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3811                                     BGE_MACMODE_TBI_SEND_CFGS);
3812                         }
3813                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3814
3815                         if (bootverbose)
3816                                 if_printf(ifp, "link UP\n");
3817
3818                         ifp->if_link_state = LINK_STATE_UP;
3819                         if_link_state_change(ifp);
3820                 }
3821         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3822                 if (sc->bnx_link) {
3823                         sc->bnx_link = 0;
3824
3825                         if (bootverbose)
3826                                 if_printf(ifp, "link DOWN\n");
3827
3828                         ifp->if_link_state = LINK_STATE_DOWN;
3829                         if_link_state_change(ifp);
3830                 }
3831         }
3832
3833 #undef PCS_ENCODE_ERR
3834
3835         /* Clear the attention. */
3836         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3837             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3838             BGE_MACSTAT_LINK_CHANGED);
3839 }
3840
3841 static void
3842 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3843 {
3844         struct ifnet *ifp = &sc->arpcom.ac_if;
3845         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3846
3847         mii_pollstat(mii);
3848         bnx_miibus_statchg(sc->bnx_dev);
3849
3850         if (bootverbose) {
3851                 if (sc->bnx_link)
3852                         if_printf(ifp, "link UP\n");
3853                 else
3854                         if_printf(ifp, "link DOWN\n");
3855         }
3856
3857         /* Clear the attention. */
3858         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3859             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3860             BGE_MACSTAT_LINK_CHANGED);
3861 }
3862
3863 static void
3864 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3865 {
3866         struct ifnet *ifp = &sc->arpcom.ac_if;
3867         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3868
3869         mii_pollstat(mii);
3870
3871         if (!sc->bnx_link &&
3872             (mii->mii_media_status & IFM_ACTIVE) &&
3873             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3874                 sc->bnx_link++;
3875                 if (bootverbose)
3876                         if_printf(ifp, "link UP\n");
3877         } else if (sc->bnx_link &&
3878             (!(mii->mii_media_status & IFM_ACTIVE) ||
3879             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3880                 sc->bnx_link = 0;
3881                 if (bootverbose)
3882                         if_printf(ifp, "link DOWN\n");
3883         }
3884
3885         /* Clear the attention. */
3886         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3887             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3888             BGE_MACSTAT_LINK_CHANGED);
3889 }
3890
3891 static int
3892 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3893 {
3894         struct bnx_softc *sc = arg1;
3895
3896         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3897             &sc->bnx_rx_coal_ticks,
3898             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3899             BNX_RX_COAL_TICKS_CHG);
3900 }
3901
3902 static int
3903 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3904 {
3905         struct bnx_softc *sc = arg1;
3906
3907         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3908             &sc->bnx_tx_coal_ticks,
3909             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3910             BNX_TX_COAL_TICKS_CHG);
3911 }
3912
3913 static int
3914 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3915 {
3916         struct bnx_softc *sc = arg1;
3917
3918         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3919             &sc->bnx_rx_coal_bds,
3920             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3921             BNX_RX_COAL_BDS_CHG);
3922 }
3923
3924 static int
3925 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3926 {
3927         struct bnx_softc *sc = arg1;
3928
3929         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3930             &sc->bnx_tx_coal_bds,
3931             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3932             BNX_TX_COAL_BDS_CHG);
3933 }
3934
3935 static int
3936 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3937 {
3938         struct bnx_softc *sc = arg1;
3939
3940         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3941             &sc->bnx_rx_coal_bds_int,
3942             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3943             BNX_RX_COAL_BDS_INT_CHG);
3944 }
3945
3946 static int
3947 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3948 {
3949         struct bnx_softc *sc = arg1;
3950
3951         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3952             &sc->bnx_tx_coal_bds_int,
3953             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3954             BNX_TX_COAL_BDS_INT_CHG);
3955 }
3956
3957 static int
3958 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3959     int coal_min, int coal_max, uint32_t coal_chg_mask)
3960 {
3961         struct bnx_softc *sc = arg1;
3962         struct ifnet *ifp = &sc->arpcom.ac_if;
3963         int error = 0, v;
3964
3965         lwkt_serialize_enter(ifp->if_serializer);
3966
3967         v = *coal;
3968         error = sysctl_handle_int(oidp, &v, 0, req);
3969         if (!error && req->newptr != NULL) {
3970                 if (v < coal_min || v > coal_max) {
3971                         error = EINVAL;
3972                 } else {
3973                         *coal = v;
3974                         sc->bnx_coal_chg |= coal_chg_mask;
3975                 }
3976         }
3977
3978         lwkt_serialize_exit(ifp->if_serializer);
3979         return error;
3980 }
3981
3982 static void
3983 bnx_coal_change(struct bnx_softc *sc)
3984 {
3985         struct ifnet *ifp = &sc->arpcom.ac_if;
3986
3987         ASSERT_SERIALIZED(ifp->if_serializer);
3988
3989         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3990                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3991                             sc->bnx_rx_coal_ticks);
3992                 DELAY(10);
3993                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3994
3995                 if (bootverbose) {
3996                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3997                                   sc->bnx_rx_coal_ticks);
3998                 }
3999         }
4000
4001         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
4002                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4003                             sc->bnx_tx_coal_ticks);
4004                 DELAY(10);
4005                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4006
4007                 if (bootverbose) {
4008                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4009                                   sc->bnx_tx_coal_ticks);
4010                 }
4011         }
4012
4013         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
4014                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4015                             sc->bnx_rx_coal_bds);
4016                 DELAY(10);
4017                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4018
4019                 if (bootverbose) {
4020                         if_printf(ifp, "rx_coal_bds -> %u\n",
4021                                   sc->bnx_rx_coal_bds);
4022                 }
4023         }
4024
4025         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
4026                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4027                             sc->bnx_tx_coal_bds);
4028                 DELAY(10);
4029                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4030
4031                 if (bootverbose) {
4032                         if_printf(ifp, "tx_coal_bds -> %u\n",
4033                                   sc->bnx_tx_coal_bds);
4034                 }
4035         }
4036
4037         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
4038                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4039                     sc->bnx_rx_coal_bds_int);
4040                 DELAY(10);
4041                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
4042
4043                 if (bootverbose) {
4044                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
4045                             sc->bnx_rx_coal_bds_int);
4046                 }
4047         }
4048
4049         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
4050                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4051                     sc->bnx_tx_coal_bds_int);
4052                 DELAY(10);
4053                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4054
4055                 if (bootverbose) {
4056                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
4057                             sc->bnx_tx_coal_bds_int);
4058                 }
4059         }
4060
4061         sc->bnx_coal_chg = 0;
4062 }
4063
4064 static void
4065 bnx_intr_check(void *xsc)
4066 {
4067         struct bnx_softc *sc = xsc;
4068         struct ifnet *ifp = &sc->arpcom.ac_if;
4069         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
4070
4071         lwkt_serialize_enter(ifp->if_serializer);
4072
4073         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
4074
4075         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4076                 lwkt_serialize_exit(ifp->if_serializer);
4077                 return;
4078         }
4079
4080         if (sblk->bge_idx[0].bge_rx_prod_idx != sc->bnx_rx_saved_considx ||
4081             sblk->bge_idx[0].bge_tx_cons_idx != sc->bnx_tx_saved_considx) {
4082                 if (sc->bnx_rx_check_considx == sc->bnx_rx_saved_considx &&
4083                     sc->bnx_tx_check_considx == sc->bnx_tx_saved_considx) {
4084                         if (!sc->bnx_intr_maylose) {
4085                                 sc->bnx_intr_maylose = TRUE;
4086                                 goto done;
4087                         }
4088                         if (bootverbose)
4089                                 if_printf(ifp, "lost interrupt\n");
4090                         bnx_msi(sc);
4091                 }
4092         }
4093         sc->bnx_intr_maylose = FALSE;
4094         sc->bnx_rx_check_considx = sc->bnx_rx_saved_considx;
4095         sc->bnx_tx_check_considx = sc->bnx_tx_saved_considx;
4096
4097 done:
4098         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
4099             bnx_intr_check, sc);
4100         lwkt_serialize_exit(ifp->if_serializer);
4101 }
4102
4103 static void
4104 bnx_enable_intr(struct bnx_softc *sc)
4105 {
4106         struct ifnet *ifp = &sc->arpcom.ac_if;
4107
4108         lwkt_serialize_handler_enable(ifp->if_serializer);
4109
4110         /*
4111          * Enable interrupt.
4112          */
4113         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
4114         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4115                 /* XXX Linux driver */
4116                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
4117         }
4118
4119         /*
4120          * Unmask the interrupt when we stop polling.
4121          */
4122         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4123             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4124
4125         /*
4126          * Trigger another interrupt, since above writing
4127          * to interrupt mailbox0 may acknowledge pending
4128          * interrupt.
4129          */
4130         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4131
4132         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
4133                 sc->bnx_intr_maylose = FALSE;
4134                 sc->bnx_rx_check_considx = 0;
4135                 sc->bnx_tx_check_considx = 0;
4136
4137                 if (bootverbose)
4138                         if_printf(ifp, "status tag bug workaround\n");
4139
4140                 /* 10ms check interval */
4141                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
4142                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
4143         }
4144 }
4145
4146 static void
4147 bnx_disable_intr(struct bnx_softc *sc)
4148 {
4149         struct ifnet *ifp = &sc->arpcom.ac_if;
4150
4151         /*
4152          * Mask the interrupt when we start polling.
4153          */
4154         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4155             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4156
4157         /*
4158          * Acknowledge possible asserted interrupt.
4159          */
4160         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4161
4162         callout_stop(&sc->bnx_intr_timer);
4163         sc->bnx_intr_maylose = FALSE;
4164         sc->bnx_rx_check_considx = 0;
4165         sc->bnx_tx_check_considx = 0;
4166
4167         sc->bnx_npoll.ifpc_stcount = 0;
4168
4169         lwkt_serialize_handler_disable(ifp->if_serializer);
4170 }
4171
4172 static int
4173 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4174 {
4175         uint32_t mac_addr;
4176         int ret = 1;
4177
4178         mac_addr = bnx_readmem_ind(sc, 0x0c14);
4179         if ((mac_addr >> 16) == 0x484b) {
4180                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4181                 ether_addr[1] = (uint8_t)mac_addr;
4182                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4183                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4184                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4185                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4186                 ether_addr[5] = (uint8_t)mac_addr;
4187                 ret = 0;
4188         }
4189         return ret;
4190 }
4191
4192 static int
4193 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4194 {
4195         int mac_offset = BGE_EE_MAC_OFFSET;
4196
4197         if (BNX_IS_5717_PLUS(sc)) {
4198                 int f;
4199
4200                 f = pci_get_function(sc->bnx_dev);
4201                 if (f & 1)
4202                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4203                 if (f > 1)
4204                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4205         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
4206                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4207         }
4208
4209         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4210 }
4211
4212 static int
4213 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4214 {
4215         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4216                 return 1;
4217
4218         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4219                                ETHER_ADDR_LEN);
4220 }
4221
4222 static int
4223 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4224 {
4225         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4226                 /* NOTE: Order is critical */
4227                 bnx_get_eaddr_mem,
4228                 bnx_get_eaddr_nvram,
4229                 bnx_get_eaddr_eeprom,
4230                 NULL
4231         };
4232         const bnx_eaddr_fcn_t *func;
4233
4234         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4235                 if ((*func)(sc, eaddr) == 0)
4236                         break;
4237         }
4238         return (*func == NULL ? ENXIO : 0);
4239 }
4240
4241 /*
4242  * NOTE: 'm' is not freed upon failure
4243  */
4244 struct mbuf *
4245 bnx_defrag_shortdma(struct mbuf *m)
4246 {
4247         struct mbuf *n;
4248         int found;
4249
4250         /*
4251          * If device receive two back-to-back send BDs with less than
4252          * or equal to 8 total bytes then the device may hang.  The two
4253          * back-to-back send BDs must in the same frame for this failure
4254          * to occur.  Scan mbuf chains and see whether two back-to-back
4255          * send BDs are there.  If this is the case, allocate new mbuf
4256          * and copy the frame to workaround the silicon bug.
4257          */
4258         for (n = m, found = 0; n != NULL; n = n->m_next) {
4259                 if (n->m_len < 8) {
4260                         found++;
4261                         if (found > 1)
4262                                 break;
4263                         continue;
4264                 }
4265                 found = 0;
4266         }
4267
4268         if (found > 1)
4269                 n = m_defrag(m, MB_DONTWAIT);
4270         else
4271                 n = m;
4272         return n;
4273 }
4274
4275 static void
4276 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4277 {
4278         int i;
4279
4280         BNX_CLRBIT(sc, reg, bit);
4281         for (i = 0; i < BNX_TIMEOUT; i++) {
4282                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4283                         return;
4284                 DELAY(100);
4285         }
4286 }
4287
4288 static void
4289 bnx_link_poll(struct bnx_softc *sc)
4290 {
4291         uint32_t status;
4292
4293         status = CSR_READ_4(sc, BGE_MAC_STS);
4294         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4295                 sc->bnx_link_evt = 0;
4296                 sc->bnx_link_upd(sc, status);
4297         }
4298 }
4299
4300 static void
4301 bnx_enable_msi(struct bnx_softc *sc)
4302 {
4303         uint32_t msi_mode;
4304
4305         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4306         msi_mode |= BGE_MSIMODE_ENABLE;
4307         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4308                 /*
4309                  * NOTE:
4310                  * 5718-PG105-R says that "one shot" mode
4311                  * does not work if MSI is used, however,
4312                  * it obviously works.
4313                  */
4314                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4315         }
4316         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4317 }
4318
4319 static uint32_t
4320 bnx_dma_swap_options(struct bnx_softc *sc)
4321 {
4322         uint32_t dma_options;
4323
4324         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4325             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4326 #if BYTE_ORDER == BIG_ENDIAN
4327         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4328 #endif
4329         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4330             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4331                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4332                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4333                     BGE_MODECTL_HTX2B_ENABLE;
4334         }
4335         return dma_options;
4336 }
4337
4338 static int
4339 bnx_setup_tso(struct bnx_softc *sc, struct mbuf **mp,
4340     uint16_t *mss0, uint16_t *flags0)
4341 {
4342         struct mbuf *m;
4343         struct ip *ip;
4344         struct tcphdr *th;
4345         int thoff, iphlen, hoff, hlen;
4346         uint16_t flags, mss;
4347
4348         m = *mp;
4349         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4350
4351         hoff = m->m_pkthdr.csum_lhlen;
4352         iphlen = m->m_pkthdr.csum_iphlen;
4353         thoff = m->m_pkthdr.csum_thlen;
4354
4355         KASSERT(hoff > 0, ("invalid ether header len"));
4356         KASSERT(iphlen > 0, ("invalid ip header len"));
4357         KASSERT(thoff > 0, ("invalid tcp header len"));
4358
4359         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4360                 m = m_pullup(m, hoff + iphlen + thoff);
4361                 if (m == NULL) {
4362                         *mp = NULL;
4363                         return ENOBUFS;
4364                 }
4365                 *mp = m;
4366         }
4367         ip = mtodoff(m, struct ip *, hoff);
4368         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4369
4370         mss = m->m_pkthdr.tso_segsz;
4371         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4372
4373         ip->ip_len = htons(mss + iphlen + thoff);
4374         th->th_sum = 0;
4375
4376         hlen = (iphlen + thoff) >> 2;
4377         mss |= ((hlen & 0x3) << 14);
4378         flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4379
4380         *mss0 = mss;
4381         *flags0 = flags;
4382
4383         return 0;
4384 }