2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <sys/thread2.h>
35 #include <machine/pmap.h>
36 #include <machine_base/icu/icu_var.h>
37 #include <machine_base/apic/lapic.h>
38 #include <machine_base/apic/ioapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
41 #define IOAPIC_COUNT_MAX 16
42 #define IOAPIC_ID_MASK (IOAPIC_COUNT_MAX - 1)
45 extern pt_entry_t *SMPpt;
54 TAILQ_ENTRY(ioapic_info) io_link;
56 TAILQ_HEAD(ioapic_info_list, ioapic_info);
58 struct ioapic_intsrc {
60 enum intr_trigger int_trig;
61 enum intr_polarity int_pola;
65 struct ioapic_info_list ioc_list;
66 struct ioapic_intsrc ioc_intsrc[16]; /* XXX magic number */
69 static int ioapic_config(void);
70 static void ioapic_setup(const struct ioapic_info *);
71 static int ioapic_alloc_apic_id(int);
72 static void ioapic_set_apic_id(const struct ioapic_info *);
73 static void ioapic_gsi_setup(int);
74 static const struct ioapic_info *
75 ioapic_gsi_search(int);
76 static void ioapic_pin_prog(void *, int, int,
77 enum intr_trigger, enum intr_polarity, uint32_t);
79 static struct ioapic_conf ioapic_conf;
81 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
82 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
84 int ioapic_enable = 1; /* I/O APIC is enabled by default */
89 struct ioapic_info *info;
90 int start_apic_id = 0;
91 struct ioapic_enumerator *e;
95 TAILQ_INIT(&ioapic_conf.ioc_list);
96 /* XXX magic number */
97 for (i = 0; i < 16; ++i)
98 ioapic_conf.ioc_intsrc[i].int_gsi = -1;
101 TUNABLE_INT_FETCH("hw.ioapic_probe", &probe);
103 kprintf("IOAPIC: warning I/O APIC will not be probed\n");
107 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
108 error = e->ioapic_probe(e);
113 kprintf("IOAPIC: can't find I/O APIC\n");
123 * Switch to I/O APIC MachIntrABI and reconfigure
124 * the default IDT entries.
126 MachIntrABI = MachIntrABI_IOAPIC;
127 MachIntrABI.setdefault();
129 e->ioapic_enumerate(e);
135 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
138 if (i > IOAPIC_COUNT_MAX) /* XXX magic number */
139 panic("ioapic_config: more than 16 I/O APIC\n");
144 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
147 apic_id = ioapic_alloc_apic_id(start_apic_id);
148 if (apic_id == NAPICID) {
149 kprintf("IOAPIC: can't alloc APIC ID for "
150 "%dth I/O APIC\n", info->io_idx);
153 info->io_apic_id = apic_id;
155 start_apic_id = apic_id + 1;
159 * xAPIC allows I/O APIC's APIC ID to be same
160 * as the LAPIC's APIC ID
162 kprintf("IOAPIC: use xAPIC model to alloc APIC ID "
165 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
166 info->io_apic_id = info->io_idx;
170 * Warning about any GSI holes
172 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
173 const struct ioapic_info *prev_info;
175 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
176 if (prev_info != NULL) {
177 if (info->io_gsi_base !=
178 prev_info->io_gsi_base + prev_info->io_npin) {
179 kprintf("IOAPIC: warning gsi hole "
181 prev_info->io_gsi_base +
183 info->io_gsi_base - 1);
189 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
190 kprintf("IOAPIC: idx %d, apic id %d, "
191 "gsi base %d, npin %d\n",
202 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
204 ioapic_abi_fixup_irqmap();
208 MachIntrABI.cleanup();
216 ioapic_enumerator_register(struct ioapic_enumerator *ne)
218 struct ioapic_enumerator *e;
220 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
221 if (e->ioapic_prio < ne->ioapic_prio) {
222 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
226 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
230 ioapic_add(void *addr, int gsi_base, int npin)
232 struct ioapic_info *info, *ninfo;
235 gsi_end = gsi_base + npin - 1;
236 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
237 if ((gsi_base >= info->io_gsi_base &&
238 gsi_base < info->io_gsi_base + info->io_npin) ||
239 (gsi_end >= info->io_gsi_base &&
240 gsi_end < info->io_gsi_base + info->io_npin)) {
241 panic("ioapic_add: overlapped gsi, base %d npin %d, "
242 "hit base %d, npin %d\n", gsi_base, npin,
243 info->io_gsi_base, info->io_npin);
245 if (info->io_addr == addr)
246 panic("ioapic_add: duplicated addr %p\n", addr);
249 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
250 ninfo->io_addr = addr;
251 ninfo->io_npin = npin;
252 ninfo->io_gsi_base = gsi_base;
253 ninfo->io_apic_id = -1;
256 * Create IOAPIC list in ascending order of GSI base
258 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
259 ioapic_info_list, io_link) {
260 if (ninfo->io_gsi_base > info->io_gsi_base) {
261 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
262 info, ninfo, io_link);
267 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
271 ioapic_intsrc(int irq, int gsi, enum intr_trigger trig, enum intr_polarity pola)
273 struct ioapic_intsrc *int_src;
276 int_src = &ioapic_conf.ioc_intsrc[irq];
279 /* Don't allow mixed mode */
280 kprintf("IOAPIC: warning intsrc irq %d -> gsi 0\n", irq);
284 if (int_src->int_gsi != -1) {
285 if (int_src->int_gsi != gsi) {
286 kprintf("IOAPIC: warning intsrc irq %d, gsi "
287 "%d -> %d\n", irq, int_src->int_gsi, gsi);
289 if (int_src->int_trig != trig) {
290 kprintf("IOAPIC: warning intsrc irq %d, trig "
292 intr_str_trigger(int_src->int_trig),
293 intr_str_trigger(trig));
295 if (int_src->int_pola != pola) {
296 kprintf("IOAPIC: warning intsrc irq %d, pola "
298 intr_str_polarity(int_src->int_pola),
299 intr_str_polarity(pola));
302 int_src->int_gsi = gsi;
303 int_src->int_trig = trig;
304 int_src->int_pola = pola;
308 ioapic_set_apic_id(const struct ioapic_info *info)
313 id = ioapic_read(info->io_addr, IOAPIC_ID);
316 id |= (info->io_apic_id << 24);
318 ioapic_write(info->io_addr, IOAPIC_ID, id);
323 id = ioapic_read(info->io_addr, IOAPIC_ID);
324 apic_id = (id & APIC_ID_MASK) >> 24;
327 * I/O APIC ID is a 4bits field
329 if ((apic_id & IOAPIC_ID_MASK) !=
330 (info->io_apic_id & IOAPIC_ID_MASK)) {
331 panic("ioapic_set_apic_id: can't set apic id to %d, "
332 "currently set to %d\n", info->io_apic_id, apic_id);
337 ioapic_gsi_setup(int gsi)
339 enum intr_trigger trig;
340 enum intr_polarity pola;
346 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
347 ioapic_gsi_pin(gsi), 0);
352 trig = 0; /* silence older gcc's */
353 pola = 0; /* silence older gcc's */
355 for (irq = 0; irq < 16; ++irq) {
356 const struct ioapic_intsrc *int_src =
357 &ioapic_conf.ioc_intsrc[irq];
359 if (gsi == int_src->int_gsi) {
360 trig = int_src->int_trig;
361 pola = int_src->int_pola;
368 trig = INTR_TRIGGER_EDGE;
369 pola = INTR_POLARITY_HIGH;
371 trig = INTR_TRIGGER_LEVEL;
372 pola = INTR_POLARITY_LOW;
377 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
381 ioapic_gsi_ioaddr(int gsi)
383 const struct ioapic_info *info;
385 info = ioapic_gsi_search(gsi);
386 return info->io_addr;
390 ioapic_gsi_pin(int gsi)
392 const struct ioapic_info *info;
394 info = ioapic_gsi_search(gsi);
395 return gsi - info->io_gsi_base;
398 static const struct ioapic_info *
399 ioapic_gsi_search(int gsi)
401 const struct ioapic_info *info;
403 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
404 if (gsi >= info->io_gsi_base &&
405 gsi < info->io_gsi_base + info->io_npin)
408 panic("ioapic_gsi_search: no I/O APIC\n");
412 ioapic_gsi(int idx, int pin)
414 const struct ioapic_info *info;
416 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
417 if (info->io_idx == idx)
422 if (pin >= info->io_npin)
424 return info->io_gsi_base + pin;
428 ioapic_extpin_setup(void *addr, int pin, int vec)
430 ioapic_pin_prog(addr, pin, vec,
431 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
435 ioapic_extpin_gsi(void)
441 ioapic_pin_setup(void *addr, int pin, int vec,
442 enum intr_trigger trig, enum intr_polarity pola)
445 * Always clear an I/O APIC pin before [re]programming it. This is
446 * particularly important if the pin is set up for a level interrupt
447 * as the IOART_REM_IRR bit might be set. When we reprogram the
448 * vector any EOI from pending ints on this pin could be lost and
449 * IRR might never get reset.
451 * To fix this problem, clear the vector and make sure it is
452 * programmed as an edge interrupt. This should theoretically
453 * clear IRR so we can later, safely program it as a level
456 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
458 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
462 ioapic_pin_prog(void *addr, int pin, int vec,
463 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
465 uint32_t flags, target;
468 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
470 select = IOAPIC_REDTBL0 + (2 * pin);
472 flags = ioapic_read(addr, select) & IOART_RESV;
473 flags |= IOART_INTMSET | IOART_DESTPHY;
478 * We only support limited I/O APIC mixed mode,
479 * so even for ExtINT, we still use "fixed"
482 flags |= IOART_DELFIXED;
485 if (del_mode == IOART_DELEXINT) {
486 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
487 pola == INTR_POLARITY_CONFORM);
488 flags |= IOART_TRGREDG | IOART_INTAHI;
491 case INTR_TRIGGER_EDGE:
492 flags |= IOART_TRGREDG;
495 case INTR_TRIGGER_LEVEL:
496 flags |= IOART_TRGRLVL;
499 case INTR_TRIGGER_CONFORM:
500 panic("ioapic_pin_prog: trig conform is not "
504 case INTR_POLARITY_HIGH:
505 flags |= IOART_INTAHI;
508 case INTR_POLARITY_LOW:
509 flags |= IOART_INTALO;
512 case INTR_POLARITY_CONFORM:
513 panic("ioapic_pin_prog: pola conform is not "
518 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
519 target |= (CPUID_TO_APICID(0) << IOART_HI_DEST_SHIFT) &
522 ioapic_write(addr, select, flags | vec);
523 ioapic_write(addr, select + 1, target);
527 ioapic_setup(const struct ioapic_info *info)
531 ioapic_set_apic_id(info);
533 for (i = 0; i < info->io_npin; ++i)
534 ioapic_gsi_setup(info->io_gsi_base + i);
538 ioapic_alloc_apic_id(int start)
541 const struct ioapic_info *info;
542 int apic_id, apic_id16;
544 apic_id = lapic_unused_apic_id(start);
545 if (apic_id == NAPICID) {
546 kprintf("IOAPIC: can't find unused APIC ID\n");
549 apic_id16 = apic_id & IOAPIC_ID_MASK;
552 * Check against other I/O APIC's APIC ID's lower 4bits.
554 * The new APIC ID will have to be different from others
555 * in the lower 4bits, no matter whether xAPIC is used
558 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
559 if (info->io_apic_id == -1) {
563 if ((info->io_apic_id & IOAPIC_ID_MASK) == apic_id16)
569 kprintf("IOAPIC: APIC ID %d has same lower 4bits as "
570 "%dth I/O APIC, keep searching...\n",
571 apic_id, info->io_idx);
575 panic("ioapic_unused_apic_id: never reached\n");
579 ioapic_map(vm_paddr_t pa)
581 KKASSERT(pa < 0x100000000LL);
582 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
586 ioapic_sysinit(void *dummy __unused)
593 KASSERT(lapic_enable, ("I/O APIC is enabled, but LAPIC is disabled\n"));
594 error = ioapic_config();
597 icu_reinit_noioapic();
598 lapic_fixup_noioapic();
601 SYSINIT(ioapic, SI_BOOT2_IOAPIC, SI_ORDER_FIRST, ioapic_sysinit, NULL)